September 25, 2014 – The APL’s AREA Consortium will present four papers at the SMTAi technical conference. In session on Oct 1, Dr. Martin Anselm is going to talk about Component Warpage: Issues with Measurement and Standardization. In the Lead-Free Symposium on Oct 2, three individual papers will be presented on the topic of Material Evaluation for High Reliability Applications.
Abstracts:
Component Warpage: Issues with Measurement and Standardization
Component warpage is the root cause for many manufacturing defects encountered by Contract Manufactures (CMs) who develop processes for the assembly of advanced products. Current JEDEC JESD22-B112A and JEITA ED-7306 standards for package warpage at elevated temperature describe the measurement techniques and provide maximum warpage recommendation for FBGA and FLGA devices. Historically only the JEITA standard defines the maximum allowable elevated temperature warpage conditions for FBGAs and FLGAs. The limitation of these standards is that defining the component warpage as an absolute is not acceptable for many of the instances where Head in Pillow (HiP) failures are observed in production. For example, there are many devices that easily comply with the standards, as characterized utilizing the prescribed techniques, yet still produce HiP failures. This is observed even in situations where contamination is an unlikely cause. The intent of this paper is to describe the limitations in measurement and complexity of warpage related defects. Several case studies are used to highlight the limitations of current industry standards and to serve as a launching point for research topics into warpage induced defects.
Low Loss Laminate Material Pad Cratering Resistance
As cloud computing applies greater and greater demands on signal speed and data transfer rates, our Telecomm industry has to pass along greater electrical performance demands on our PCB laminate material suppliers. However what mechanical performance do these high cost materials exhibit? The answer is largely untested. This report compares the pad cratering performance of one commonly used material and two low loss materials utilized in many HDI and high speed product applications. A four-point cyclic bend test was used to compare the pad cratering resistance of three printed circuit board materials; Isola 370HR, Arlon 44N and Panasonic Megtron 6.
Effect of PCB Surface Finish on Sn Grain Morphology and Thermal Fatigue Performance of SnPb and Lead Free Solder Joints
Continuous decrease in the size of components brings new reliability challenges as the microstructure of lead-free solder alloys is significantly affected by solder volume. It is well known that the microstructure of solder joints greatly affect the reliability of electronic packages. In our current work, different PCB surface finishes such as ENTEK-OM and direct palladium are compared to Cu OSP. These surface finishes do not contain a Ni barrier layer and therefore are being considered by the high speed and RF markets for their superior electrical performance. However the effects of second level solder joint reliability are not well understood. The impact of those various surface finishes on the microstructure of SAC305 lead-free LGAs, BGAs and CSPs, were investigated. In addition, results were compared to packages reflowed with conventional eutectic SnPb alloy. A comprehensive microstructural investigation was performed to understand the effect of Sn grain morphology on failure mechanism in accelerated thermal cycling (ATC) test. Sn grain morphology was characterized by polarized light microscopy (PLM) and electron backscatter diffraction (EBSD). The effect of surface finish on Sn grain morphology and lifetime was assessed.
A clear correlation between PCB surface finish, microstructure and reliability behavior was observed. The effect of various Sn grain morphologies on reliability performance was discussed. The results assist in optimizing the design of packages and selection of materials that can lead to higher reliability performance of products.
Component Level Testing of Thermal Interface Materials
While component footprint size continues to decrease year after year, power dissipation continues to increase. Thermal interface materials (TIMs) are frequently used to increase the efficiency of heat transfer from the die to the thermal solution. However selection of a gap pad material can be problematic because the manufacturer’s data is often unreliable, differing considerably from what is encountered in the field. Additionally the standard for measuring thermal resistance of gap pad materials, ASTM D-5470, is flawed because of unrealistic loading conditions and contact resistances.
In an effort to provide more realistic thermal resistance measurements, a variable load component level test fixture was developed for measuring the thermal resistance of TIMs. The thermal resistance of 14 commercially available gap pads was measured at 10%, 30% and 50% compression. Thermal resistance measurements were compared to data published by the manufacturer. The microstructure of each gap pad was also studied in conjunction with thermal resistance measurements to help explain TIM performance.
If you wish to learn more about the AREA Consortium or becoming a member, visit http://www.uic-apl.com/area-consortium or contact either Denis Barbini (barbini@uic.com/+1 603-828-2289) or David Vicari (vicari@uic.com/ +1 607-779-5151).
