AREA CONSORTIUM REPORTS

2008 REPORTS

2008 Overview
Author: Peter Borgesen

Abstract:This document offers a brief summary of our 2008 efforts. Details of the work and results are found in the individual reports or presentations referred to below, or in reports and presentations cited in those.

Microstructure Evolution in Pb-Free Solder Alloys During Isothermal Aging
Author: Liang Yin

Abstract: In order to test reliability of solder joints being put in storage or service for certain time, preconditioning of as-reflowed solder joints is needed by isothermal aging at higher temperatures. Sn-Ag-Cu lead free alloys are composed with more phases than the eutectic SnPb alloy. In this report, isothermal aging was conducted at 125°C up to 14 weeks for SAC405 solder bumps on Cu pads. Two secondary precipitates of Cu6Sn5 and Ag3Sn were seen to coarsen at different rate. The implication is that preconditioning might not produce the exact microstructure and mechanical behavior of solder joints stored at room temperature of long time. The evolution of β-Sn dendritic and grain structure were also monitored during aging.

Effect of Bath Agitation on Voiding in Cu3Sn
Author: Liang Yin

Abstract: As one of the Cu electroplating process parameters, bath agitation could affect the mass and charge transfer mechanisms on the solution/cathode interface. The effect of bath agitation on the propensity for voiding in Cu3Sn was evaluated in a rotating disc electrode (RDE) setup, by varying the rotation speed. Two generic plating additive systems were investigated at room temperature under various current densities. One system contained poly-ethylene glycol (PEG) and chloride ions (Cl-); the other contained bis-(3-sulfopropyl) disulfide (SPS), PEG and Cl-. In both additive systems, over-potential was observed to decrease with rotation speed. The correlation of over-potential versus voiding level was consistent with our current voiding hypothesis.

Microstructure Evolution in Pb-Free Solder Alloys During Thermal Cycling
Authors: Liang Yin and Yan Xing

Abstract: Accelerated thermal cycling (ATC) test is usually used to evaluate solder joint reliability under cyclic temperature variation. In such test, deformation and failure of solder joints depend on solder microstructure, which evolves with time during ATC. In order to better correlate the ATC results with fatigue life under service conditions, it is important to identify microstructure changes and their effects on crack initiation and propagation. In present report, SAC205 and SAC305 solder joints were evaluated after thermal cycling with various dwell times. Grain structure, dendritic structure, recrystallization and Ag3Sn precipitate coarsening were compared. Cyclic strain was seen to result in several unique microstructural changes during thermal cycling

Additive Replenishment and Voiding in Cu3Sn
Author: Liang Yin

Abstract: Voiding propensity of electroplated Cu has shown to be dependent on additive chemistry and plating parameters, such as current density, bath temperature and bath age. A previous consortium study has shown that in a suppressor-brightener additive system excess brightener during plating could lead to a sudden surge of void propensity. The present report focuses on the effect of bath age on the stability of plating process after additive replenishments. Potential transient and voiding behavior were monitored for samples plated at a current density of 10 mA/cm2 with single and multiple replenishments of the brightener and the suppressor. Xray diffraction (XRD) was also utilized to exam the texture evolution with bath age.

Controlling Cu Electroplating to Prevent Sporadic Voiding in Cu3Sn
Authors: Liang Yin, Pericles Kondos, Peter Borgesen, Yihua Liu, Stoyan Bliznakov, Fred Wafula, Nikolay Dimitrov, Donald Henderson, Christopher Parks, Mao Gao, Joseph Therriault, Ju Wang and Eric Cotts

Abstract: One reliability concern, when soldering to a Cu surface finish, is the sporadic mechanical degradation of solder joints due to the formation and growth of voids within the interfacial Cu3Sn intermetallic compound (IMC) layer and at its interface with the Cu pad structure. Excess organic impurity incorporation during Cu electroplating has been shown to cause this problem. The level of impurity incorporation is found to depend greatly on interactions between the plating additive chemistry and the plating process parameters. A general picture has been developed, based upon the parabolic adsorption behavior of organic molecules on metal electrodes in aqueous plating solutions as a function of the applied potential. Thus the propensity for voiding, in soldering and subsequent thermal aging, can be manipulated by varying a range of plating parameters. The mechanistic understanding required to devise practical control is outlined. Any remaining research required for the formulation of step-by-step process guidelines is identified.

A Case Study of Sporadic Brittle Failure on Ni/Au Surface Finish
Author: Liang Yin

Abstract: The report presents a case study of sporadic brittle failure on Ni/Au surface finish of a ball grid array (BGA) package. Metallurgical analysis and a series of mechanical tests were used. Results were compared between 2 production lots.

Effect of Suppressor Molecular Weight on Voiding in Cu3Sn
Author: Liang Yin

Abstract: Typical additive systems for acid Cu plating are often composed of a suppressor and a brightener. The molecular weight of suppressor plays an important role of maintaining the stability of plating process. Samples were plated with a typical suppressor of poly-ethylene glycol (PEG) with molecular weight ranging from 600-4000 g/mol in plating solutions with and without a brightener of bis-(3-sulfopropyl)-disulfide (SPS). Plating transients and voiding behavior were monitored with bath age. In the bath did not contain SPS, plating with lower molecular weight showed less suppressing effect and less voiding level. In the bath contained SPS, plating with lower molecular weight led to less polarization and faster SPS consumption.

Analyzing Thermal Cycle Parameters with “Low Reliability” Packages
Authors: Michael Meilunas and Emad Al-Momani

Abstract: Understanding how accelerated thermal cycle parameters such as temperature extremes and dwell time affect the reliability of a lead-free solder joint is an important focus of the AREA Consortium and, in general, the effects of cycle parameters are now know. However a method is desired which can be used to scale between various thermal cycle parameters so that a meaningful analysis of device reliability can be performed without actually testing every cycle parameter. The following is not a discussion on the scaling technique itself, but rather a full documentation of the various accelerated test results used to create and refine the technique.

Evaluating Low I/O BGAs, MLFs, and Other Surface Mount Devices
Authors: Michael Meilunas and Emad Al-Momani

Abstract: This report summarizes the assembly processes, experimental procedures and thermal cycle testing results for multiple surface mount devices assembled with tin-lead and lead-free solder alloys. Other parameters investigated included edge bonding, printed circuit board pad diameter and via technologies. Two thermal cycle profiles were used to stress the assemblies: a 0/100oC cycle with 10 minute temperature dwells and a 0/100oC cycle with 60 minute temperature dwells.

Backward Compatible Fine Pitch CSP Build and Thermal Cycling With and Without Underfill: 2008
Authors: Daniel Blass and Michael Meilunas

Abstract: A variety of 0.4 and 0.5mm pitch CSPs were built with a SnPb solder paste. Component ball alloy was either eutectic SnPb or Pb-free (SAC305 or SAC405). Both SnPb and Pb-free versions of several components were assembled while the remaining components were available in either SnPb or SAC. The six layer PCB measured roughly 14” x 17” and was 2mm thick and had a Cu-OSP pad finish. Some of the components were underfilled with Emerson and Cuming E1159 reworkable CSP underfill. Unlike most reworkable CSP underfills, the glass transition temperature (Tg) is relatively high at 105°C and the storage modulus is 2.7GPa. Thermal cycling was conducted with 15 minute dwells at 0°C and 100°C. The results prove that the selected underfill can significantly improve the reliability of the SnPb assemblies tested, but significantly reduces the reliability of the mixed solder (SnPb + SAC) assemblies tested.

Mixed Solder Alloy Reliability
Author: Michael Meilunas

Abstract: Backward compatible soldering is a process in which Pb-free devices are assembled to PCBs using SnPb paste resulting in “mixed” alloy solder joints. This report discusses the reliability of three backward compatible assemblies evaluated in 0/100oC thermal cycles with 10, 30 and 60 minute dwell times and -40/125oC thermal cycles with 10 and 60 minute dwell times. Results were compared to identical SAC305 samples assembled and tested in a similar manner. The findings strongly suggest that the mixed alloy stress relief process is not as sensitive to the thermal cycle test parameters as is SAC305.

Optimizing PCB and Stencil Designs to Reduce Thermal Pad Voiding in QFN Assemblies
Authors: Michael Meilunas and Emad Al-Momani

Abstract: Quad Flat No-Lead (QFN) packages contain exposed die attach paddles to provide efficient heat paths when soldered toprinted circuit boards (PCB) [1]. Maximum heat transfer capacity occurs when the resulting solder connection is void free. However, achieving a void free solder joint is unlikely –especially when soldering large QFNs. The following report describes an experiment performed by the Unovis Solutions’ Advanced Process Lab which analyzed multiple PCB and stencil designs for a variety of QFN sizes with the specific goal of identifying design features which could be used to reduce void formation within die paddle solder joints. Several designs were found which consistently produced acceptable void levels, but no design feature was identified which could eliminate voiding altogether.

Effect of Thermal Cycle Parameters on the Reliability of Pb-free Solders
Author: Michael Meilunas

Abstract: This report is the final companion piece to “2006 Pb-Free Update: Evaluating Accelerated Thermal Test Parameters for Select Solder Alloys”[1]. The report contains all the thermal cycle testing data from [1] plus additional data generated through mid 2008. The experiment discussed in this report was designed to evaluate the reliability of four Pb-free solder alloys subjected to 0/100 and -40/125oC accelerated thermal cycles with 10, 30, 60 and/or 120 minute dwell times. The results indicate that the measured reliability of the Pb-free solders is highly dependent upon both dwell time and test temperatures.

QFN / MLF Process Guide 2008
Author: Michael Meilunas

Abstract: The following paper provides detailed design and process guidelines for Quad-flat No-Lead (QFN) packaging based on a substantial body of work performed by the AREA Consortium from early 2004 through late 2008. The information presented is designed to supplement and/or supersede the generic guidelines often offered by the device manufacturers. This is especially true for fine pitch (0.4mm) assembly. The goal of this process guide is to improve first pass assembly yields while maintaining or improving the long-term reliability of the QFN devices. Recommendations concerning printed circuit board design, stencil design, and pick and place operations are discussed. The information presented is based on actual experimentation, but due to the many QFN design variations available, it is up to the end user to verify that a good, reliable assembly is achieved before incorporating the recommendations into a final product.

Reliability Analysis of a Leadless Power Module
Authors: Michael Meilunas, Emad Al-Momani and Timothy Levo

Abstract: This report summarizes the assembly processes, experimental procedures and testing results for a leadless surface mount power module acquired with four solder plating variants.

Thermal Cycle Results for Surface Mount Packages on SJRB 2008
Authors: Michael Meilunas and Emad Al-Momani

Abstract: Solder Joint Reliability Board 2008 (SJRB 2008) is a 16 layer printed circuit board designed by a consortium member for vibration and thermal cycle testing of surface mount components. The topside of the board contains 24 CSP/BGA and four TSOP footprints which were assembled at Unovis Solutions using tin-lead, lead-free and mixed solder technologies. In addition to the solder alloys, variables including PCB surface finish, underfilling and edge bonding were also evaluated through thermal cycling.

Thermal Cycle Reliability Assessment of Surface Mount Devices on Test Board 2007
Author: Michael Meilunas

Abstract: In 2007 the Unovis Solutions’ Advanced Process Lab asked AREA Consortium members to suggest lead-free surface mount devices for the upcoming 2008 thermal cycle reliability assessment program. Fifteen package designs were provided and copper OSP and ENIG motherboards were designed to accommodate the samples. The devices were assembled and testing began in March of 2008. The following report documents the basic assembly processes, test procedures and results through December 2008. Testing continues as of this writing and updated reports will be issued as necessary.

Thermal Cycling and Drop Testing of Leadless Packages Located on “QFN Process Board 2007″
Author: Michael Meilunas

Abstract: This report describes the printed circuit board, materials, assembly processes and test procedures used to evaluate 14 leadless surface mount package designs in drop tests and thermal cycling. Although testing is incomplete, the available results indicate that most of the leadless designs, when properly assembled, produce 2nd level interconnections that are quite robust.

Thermal Cycle Reliability Program 2008 Report Overview
Author: Michael Meilunas

Abstract: This overview provides a brief description of the ten main 2008 AREA Consortium thermal cycle testing program reports.

Edge and Corner Bond Evaluation in Drop Test Reliability
Authors: Brian Roggeman, Laurence Harvilchuck, and Tim Levo

Abstract: Four materials were selected for evaluating the mechanical reinforcement of edge and corner bonds on area array components. The materials were jet dispensed onto the components in lengths of approximately 15% and 35% and 100% of the component size. Drop test improvements over non-reinforced assemblies were on the order of 10-30X, with greater lifetime coming from the longer fillet lengths. Failures in the solder joints were observed only after the bond material had failed, either by cohesive cracking through the material, or by adhesive failure with the solder mask.

Using Energy as a Metric for Drop Test Reliability
Authors: Tim Levo and Brian Roggeman

Abstract: A standard JEDEC style drop test board was populated with four components at symmetric locations, and the reliability was measured in drop testing for nine different input loadings. Failure analysis proved that pad cratering was the only failure mode, so direct comparisons between inputs were made, resulting in the development of an input energy approach to predict lifetime in drop testing.

Pad Cratering in Drop Test: Solder Alloy Effect
Author: Brian Roggeman

Abstract: PCB pad cratering is a common failure mode in board level drop testing. The resistance to cratering is highly dependent on the materials used in the assembly as well as the type of loading. Previous efforts focused on the PCB laminate material and/or the pad structure itself. This report discusses the results of solder alloy selection and its effect on the drop reliability when PCB cratering is the failure mode. It was found that SAC105 results in better reliability than SAC305, even when both assemblies fail solely by cratering.

Effect of PCB Pad Size on Drop Test Reliability
Author: Brian Roggeman

Abstract: Test vehicles were designed and fabricated with four different pad sizes. The boards were assembled with model BGA/CSP components with SAC305 solder balls and subjected to standard JEDEC style drop testing. It was found that the larger pads provide for greater drop reliability. Failure modes varied between intermetallic cracking at the component side SMD pad, to pad cratering of the PCB pad, with no noticeable trends.

Investigation of Crack Propagation in Pad Cratering Failures
Authors: Gaurav Godbole and Brian Roggeman

Abstract: Pad cratering occurs by fracture of the resin underneath the solder pad. Current testing shows that this fracture is not trivial, and that damage extends past the first layer of resin and glass. The particular glass style used in the laminate, along with the orientation of that glass factor into the reliability of the pad. Using a statistical approach to quantify crack length, the crack growth rate appears to increase as the crack gets longer.

Investigation of Tin-Copper-Nickel Solder Alloy in SMT Assemblies
Authors: Ursula Marquez de Tino, Linlin Yang, Denis Barbini, Brian Roggeman and Michael Meilunas

Abstract: The Tin-Copper-Nickel (SCN) solder alloy has been widely used in wave solder applications due to its applicability in achieving acceptable solder results for many printed circuit board types. In this study, SCN alloy is characterized as a surface mount alloy to determine investigate assembly and reliability issues in this application. Reflow processes were developed for the SCN solder paste using SAC305 and SCN bumped BGA/CSP components. The characterization of the assembly was done using cross sectional and SEM analysis, mechanical testing and thermal cycling. The objective of the study was to characterize and compare the performance of pure SCN joints, pure SAC 305 joints and a mixed SCN/SAC 305 solder joint. This was accomplished by designing reflow soldering profiles that reached the same peak temperatures and time above liquidus optimized for typical SAC305 assemblies. Both the vibration and thermal cycling results suggest that SCN is similar to SAC305 in terms of reliability.

Package on Package Reliability Results
Author: Brian Roggeman, Michael Meilunas and Tim Levo

Abstract: Package on Package (PoP) presents a unique reliability concern. Both the mechanical drop and thermal cycling reliability were examined on the Amkor 14mm PoP device. Mechanical robustness was measured as a function of stacked package soldering material (i.e. flux or paste), as well as dip thickness, with paste dipping generally outperforming flux dipping. Underfill and corner bonding were found to greatly enhance the drop reliability. Accelerated thermal cycling results show that this PoP package tends to fail at the stacked package in -40-125oC thermal cycling, but failure is more likely to occur at the base package in 0-100oC thermal cycling.

Package on Package: Warpage and Assembly Characteristics of Various Devices
Author: Brian Roggeman

Abstract: The warpage of Package on Package (PoP) devices is critical to successful assembly and reliability. Four different package types were procured and measured for warpage during simulated assembly conditions, both as individual packages and pre-stacked modules. The warpage was found to correlate well with assembly defects, namely head-in-pillow failures, on one device. Both a test version as well as the production version of that package exhibited similar warpage characteristics, indicating similar mechanical properties. Both paste and flux dipping were attempted for a different package and the resultant joint heights were seen to be a function of the dip material.

Component Underfill Manual 2008
Authors: Laurence Harvilchuck, Daniel Blass and Antonio Prats

Abstract: BGA and CSP assemblies may be underfilled to protect them from mechanical shock, such as impact, drop, or bending forces. These assemblies are designed with adequate resistance to thermal fatigue for most applications, though components with either very large body sizes and/or very fine ball pitch may merit special attention. A special case is that of the Wafer Level Chip Scale Package (WLCSP). The CTE mismatch of the WLCSP and an organic substrate requires underfilling for anything but the mildest thermal cycling conditions. There is also a growing tendency for designers to take advantage of the area array paradigm in more high-reliability, harsh environment applications where the thermal cycling resistance of regular BGA packages may be insufficient.

The concept of package underfill was originally developed for flip chip packages, and information in our Flip Chip Underfill Process Manual may be of utility for BGA and CSP underfill. There are, however, important differences between the underfilling of flip chips and the underfilling of packages. While underfilling invariably improves the reliability of flip chips, underfill may often end up reducing the reliability for the packages unless special measures are taken.

The present document offers, in a step-by-step approach, our present best practices regarding the development of underfill processes for BGAs and CSPs attached to a PCB with either SnPb or lead free solder joints. Preparatory work, rapid development of a process for a given application, and troubleshooting are all detailed herein. The most important step may arguably be that of materials selection, and we offer detailed recommendations as to materials selection criteria and the establishment of a materials database that may be useful for process troubleshooting.

Area Array Rework Process Manual 2008
Author: Laurence A. Harvilchuck

Revisions from 2007 to 2008:

1. Repair of Tin-Copper-Nickel (SNIC) alloy assemblies

2. Details regarding pad fatigue testing in repair evaluation

3. Additional notes on pad cratering in area array repair

4. Repair of corner/edge bonded assemblies

5. Notes on use of spot heating in PCB repair

Improved Solder Scavenging of Large Area Array Sites
Authors: Laurence Harvilchuck, Paul Austen and Paul Wood

Abstract- When removing an area array component, such as a ball-grid array (BGA) for repair, there is typically an excess of solder remaining on the board. This excess solder can cause short circuits by bridging between adjacent joints and/or open circuits by preventing the complete collapse of all joints. It is imperative that the excess solder be removed to present a uniform surface across the site for proper component attachment, as BGA rework can be both time consuming and costly. This article explores ways to improve that repair process.

Impact of PCB Pad Site Dress Methods on Pad Array Damage
Authors: Laurence Harvilchuck, Brian Roggeman, Raiyo Aspandiar, James Wade and Gaurav Godbole

Abstract- There is scant data available to the process engineer to support the choice of PCB pad site dress methods from the perspective of potential printed circuit board damage. The thermal profile experienced by the pad array can have a profound impact on latent PCB damage, including the presence or absence of pad cratering. In this exercise, pad array damage is evaluated as a function of assembly preheating, pad site dress method, and applied desoldering temperature to offer insight when choosing between simple wick-and-iron solder removal and the more sophisticated vacuum–assisted solder scavenging methods.

High-resolution sixteen channel thermal profiles were obtained of both the wick-and-iron and vacuum scavenging operations across a single 34mm square pad array of variable pitch on a 0.060” thick lead-free ATX motherboard, revealing the nature of the thermal profile at the pad surface and through the board section to the cores. The shortcomings of current repair thermometry methods are also documented in the context of the impact of thermocouple placement on profile accuracy. Process variations that are inherent in the primarily manual wick-andiron solder removal methods are readily apparent in the thermal profiles experienced by the pad array, while significantly reduced in the thermal profile generated by the vacuum scavenger.

Wick-and-iron scavenging operations can subject the pad array to ramp rates approaching 200°C/second during the brief excursion above the solder liquidus, while vacuum scavenging of the same site exhibited a maximum ramp rate nearly a full order of magnitude less but of much greater times above liquidus. The impact of the thermal profile on the pad array was characterized by bump pull, pad fatigue and dyeand-pry techniques.

The results from the present study showed no solder mask damage in the vicinity of the pad array resulted from any of the scavenging processes. Damage to inner layer circuit board structures (per the IPC-610 standard) beneath the pad array was also absent in all cases under study. Use of substrate preheating during solder scavenging has a definite impact on reducing the substrate damage that can result from the repair of lead-free laminates. For both the wick-and-iron and vacuum methods, higher applied desoldering temperatures resulted in weaker pad adhesion than the corresponding solder removal operations at lower applied desoldering temperatures. Further pad fatigue testing of the same samples indicated that this change in pad adhesion strength may be related to a change in the ductility of the laminate directly beneath the pad. While the results presented here are based on a single laminate system, the choice of laminate supplier can also have a significant impact on the propensity for substrate damage during pad site dress.

Rheology and Bondline Formation Flow Characteristics of Filled-Polymeric Thermal Interface Material Systems
Authors: David F. Rae, Eric J. Cotts and Peter Borgesen

Abstract: Thermal bondlines created with viscous filled-polymeric systems are often formed by a squeeze flow process. In order to expand our understanding of the conditions under which a material will create a laterally homogeneous or heterogeneous bondline structure, we measured the rheological characteristics of two thermal interface materials (Lord MT315, Dow Corning DA6534) in both steady rotation shear flows and in squeeze flow conditions. Using steady rotation rheometry the shear rate dependence of the sample volume under test was evaluated. Over a range of shear rates (0.01-0.3 s-1) the data fit well to a Power-Law fluid model for both materials under conditions that minimized the effects of wall slip and secondary flows in the gap. With the DA6534 material, the reproducibility of the constitutive equation parameter estimates was evaluated with various test geometries; good agreement was found between three standard steady rotation geometries (parallel plate, cone and plate, couette). For the parallel plate geometry the effect of plate surface roughness was evaluated (as machined stainless steel, with affixed abrasive papers). For both materials in squeeze flow testing, by varying the squeeze rate (0.01-10 µm/s) and/or by varying the processing temperature, we identify phase separation trends in the transient force vs. gap width data collected. The onset of heterogeneity was found to match well with a Peclet number scaling argument available from the rheology literature for the MT315 material. The final location of filler compaction regions in the bondline was visualized using X-ray transparent substrates and shown to be strong function of the initial deposit pattern selected, substrate surface finish, and the bondline formation process parameters.

Enhancement of Bondline Thermal Performance through Process Induced Heterogeneity and Compaction
Authors: David F. Rae, Eric J. Cotts and Peter Borgesen

Abstract: Great efforts are expended by researchers to develop new and better thermal interface materials. In contrast, optimization of the performance of a given material is usually left to more empirical efforts. Unfortunately, interactions between the many parameters affecting performance make the design of experiments required for empirical optimization impractically large. We are conducting systematic mechanistic studies on the combined effects of materials selection and process parameters such as normal forces, assembly speeds, and thermal profiles on bondline macro/microstructure and thermal performance.

The most common type of medium/high-performance thermal interface material is undoubtedly that of polymers filled with conductive particles, most often Ag. However, these materials rarely perform as well in a practical application as predicted based on manufacturer supplied data sheets. This is usually ascribed to defects such as voids, porosity and filler distribution heterogeneity. Such defects can be minimized by process optimization, but we also believe that we can learn to tailor some level of heterogeneity to our advantage. In fact, a thermal resistance two and a half times lower than that predicted based on the data sheet has already been demonstrated for one high-end commercial material. Moreover, this can be compatible with a practical manufacturing process.

The present paper offers a discussion of results of systematic process studies on commercial filled polymer materials, including correlations between process parameters, defects and final bondline thickness. Typical thermal conductivities of adhesives with, say, 30% Ag (by volume) are lower than that of pure Ag by a factor of fifty or more. The reason for this is that a relatively small fraction of the Ag particles are in conducting chains; in many instances heat must travel through interfaces between the Ag and thin coatings or layers of polymer. Indications are that the fraction of metallic (electron) transport (transport through chains of Ag) can be enhanced in an optimized assembly process through modification of the material deposition, bond line formation, and bond line stabilization operations.

Maintaining Thermal Bond Line Performance Following Formation: Cure or Secure
Authors: David F. Rae, Eric J. Cotts and Peter Borgesen

Abstract: Process research conducted over the AREA Consortium 2008 effort highlighted the importance of locking in the bondline structure following bondline formation with filled-polymeric thermal interface materials. This report provides a discussion of these observations. Flexure of the system during bondline formation led to relaxation after the compressive load applied during bondline formation was removed. This relaxation led to a resultant drop in performance as measured through electrical resistance monitoring. By locking in the microstructure following bondline formation through cure or mechanical secure it was found, for the material studied, that both were excellent methods of ensuring that performance was maintained.

Characterization of a Very Fine Pitch Die and its Substrate
Author: Pericles A. Kondos

Abstract: Two sets of very fine pitch die, supposedly differing only in the presence or absence of solder at the tips of their copper bumps were characterized together with their substrate. Quite a few other differences between the two die were discovered, and several issues were identified and are discussed in detail. While some of them might be unique to these die, others should be common to any die or assembly of comparable pitch and dimensions and therefore of greater general interest.

More About Brittle Failures of Joints on Electrolytic Ni/Au
Authors: Pericles A. Kondos and Pushkraj Tumne

Abstract: Experiments were conducted on SAC solder bumps with various amounts of Cu added in different ways and occasionally containing small amounts of other elements (Ni, Zn). The bumps were subjected to pull tests under conditions that caused many or all of them to fail with brittle failures in the intermetallic region. When needed, the intermetallic strength distributions were extracted from the data sets with the Kaplan-Meier method. The failure surfaces and the intermetallic microstructure and composition were also studied in detail. “Missing balls” were encountered in three instances. Board-to-board variations were observed for nominally identical substrates, but conclusions could still be drawn especially when samples came from the same board. Adding Zn led to formation of particles of a new IMC. An unexplained P-containing layer within the (Cu,Ni)6Sn5 was seen in some SAC bumps.

Very Fine Pitch Assembly Issues

Author: Pericles A. Kondos

Abstract: The issues encountered in assemblies with fine pitch die were explored, using a particular set of die and substrate as a case study. A machine capable of very accurate placement and in situ reflow was used in attempts to place this die. Issues associated with fluxing and proper aligning were resolved, and assemblies were produced, but they were very weak and fell apart very easily, preventing the continuation of the study. While individual small joints should in general be fragile, the problem was exacerbated by characteristics of this particular set of die.

Pendulum Tests: An Alternative Method for Investigating Brittle Failures of Joints on Ni/Au
Author: Pericles A. Kondos

Abstract: Periodic impact tests using a pendulum were performed on samples with SAC balls on electrolytic Ni/Au and Sn/Pb on ENIG pads. Two electrolytic Ni/Au substrate types were tested. Big differences in the number of hits until failure were seen between the two types when the failures were completely or partially in the intermetallic. Solder failures required many more hits and the difference between the two substrates was less dramatic. The ENIG results were qualitatively similar, but more difficult to interpret, pointing to a possible effect of different solder properties.

Accelerating the Effects of Aging on the Reliability of Lead Free Solder Joints in a Quantitative Fashion
Author: Vikram Venkatadri and Liang Yin

Abstract: The properties of lead free solder joints continue to change over a very long period of time in service before the microstructure becomes stable. The quantitative assessment of long term service life by accelerated testing invariably misses this significant effect, and may thus end up seriously misleading. The long term goal of the present work is to establish a protocol for preconditioning of lead free solder joints before thermal cycling or mechanical testing. For this purpose, the state of a solder joint at any given time was characterized in terms of three different room temperature properties, shear strength, shear fatigue resistance, and micro hardness. These properties were measured before and after aging for different lengths of time at different temperatures. Three common lead free alloys were selected for the present study: 98.5Sn-1.0Ag-0.5Cu (SAC105), 96.5Sn-3.0Ag-0.5Cu (SAC305), and 95.5Sn-4.0Ag-0.5Cu (SAC405). The present study did not address effects of solder volume, pad size, pad finish or reflow profile, focusing on 30 mil (760µm) diameter solder spheres reflowed onto solder mask defined OSP coated Cu pads with a typical lead free profile. Isothermal aging was conducted for up to 3,000 hours at temperatures of 70oC, 100oC, and 125oC respectively. As expected, the resulting room temperature properties all decreased with aging time, and faster so for higher aging temperatures. Some of the acceleration factors extracted for the evolution of the individual properties did, however, differ greatly for a given alloy. The only way to establish the same microstructure, and thus the same combination of properties, faster by annealing at a higher temperature is thus to fully stabilize it. This takes thousands of hours even at 125oC, i.e. it is not practical for real assemblies.