AREA CONSORTIUM REPORTS

2007 REPORTS

Package on Package (PoP) Assemblies: Underfilling and Mechanical Robustness
Authors: Daniel Blass, Michael Meilunas and Brian Roggeman

Abstract: The following report covers recent investigations into underfilling or reinforcing Package on Package (PoP) components to improve mechanical robustness. The dispensing processes were investigated for underfilling the bottom component, underfilling both components, or bonding the top component to the mold cap of the bottom part. Vibration, drop, and thermal cycle testing were performed to determine the effectiveness of the various reinforcement options. Failure analysis characterized the locations andtypes of failures that occurred. Reinforcing a particular location could help in some testing and hurt reliability in other tests.

Reinforcing CSPs with Edge and Corner Bonds of Lord MA420 Surface Mount Adhesive
Author: Daniel Blass

Abstract: A snap-cure surface mount adhesive was used to make full edge fillets and corner edge fillets that bond the edges of CSPs to the PCB. A non-contact jet dispensing process was developed for the adhesive. Full edge and 5mm long fillets at the component corners were used to reinforce SAC305 balled CSPs. Drop test improvements of 5x to 1st failure and 10-16x drops to N63 were observed. Failure of the edge fillets occurred by either delamination/fracture along the PCB solder mask or by cracks that ran through the fillet to just under the edge of the component. The solder joints tended to fracture at the ENIG PCB pad but there was also pad cratering under the PCB pads. Some solder cracking was found near the Cu component pad.

Thermal Cycle Comparison of Underfilled CSPs
Author: Daniel Blass

Abstract: Pb-free CSPs were underfilled with five different underfills and thermal cycled between -40°C and 125°C with 1 hour dwells. While all of the underfills would improve mechanical robustness and drop test performance, failure times in thermal cycling varied strongly with the underfill mechanical properties. Earliest failures occurred with CSPs underfilled with a reworkable underfill with a low glass transition temperature (Tg). Cycles to N63 for this set was half that of the non-underfilled set. Two underfills had high Tgs but no silica fillers added to reduce the thermal expansion coefficients (CTE). These two underfills gave slight improvements in N63. Components encapsulated with the two high Tg, low CTE underfills have no failures after cycling for 5 times the N63 of the nonunderfilled set.

Reliability Results for SAC305-Bumped Flip Chips in Several Thermal Cycles
Author: Daniel Blass

Abstract: SAC305-bumped flip chip assemblies were built on thin organic substrates and encapsulated with 8 underfills. The mechanical properties of the underfills varied. Assemblies were tested in three liquid shock conditions and one air thermal cycle. Two high CTE underfills gave early failure but the one with a Tg below the dwell temperature failed 3.5 to 6 times faster. Lower CTE underfills with Tg near or slightly below the dwell temperature did very well in 5 and 15 minute dwell liquid shock tests. Changing to a long dwell air to air cycle gave failure in about 25-40% as many cycles compared to the shock tests. Two higher Tg underfills with lower CTEs were tested but the failure mode was corner fillet cracking and corner delamination rather than solder joint fatigue.

Effects of Surface Finish and Assembly Process on Thermal Interface Bondline Microstructure
Authors: David F. Rae and Eric J. Cotts

Abstract: The coupled effects of surface finish and assembly process on thermal interface bondline microstructure were investigated. A silver flake filled epoxy based thermal interface material was applied between smooth or rough glass substrates. The rate of assembly and ultimate force were varied. During assembly, the temporal loading force and gap width data were collected and post cure macro and microstructures were visualized. Squeeze flow modeling using the results of rheological characterization matched well with the data collected during assembly. Surface finish had a strong effect on bondline assembly, thickness, and microstructure when slow squeeze rates were used and phase separation occurred. Phase separation behavior was observed for bondlines prepared using both the fastest and slowest sample assembly speeds. Future work will concentrate on the effects that these unique microstructures have upon thermal performance.

Crack Growth Analysis of SAC305 Solder Subjected to -40/125°C Thermal Cycling
Author: Michael Meilunas

Abstract: The crack growth rate of three similarly constructed SAC305 BGAs subjected to -40/125oC thermal cycling with 10 minute dwell times was calculated using a dye penetration measurement technique. The results for all three packages were compared to the measured lifetime of comparable components in the same thermal cycle. The experiment shows that a.) crack growth rate is relatively constant after some initial cycling and b.) the computed average crack growth rate using the dye penetration method, if used to predict the reliability of a population, would produce an average lifetime significantly greater than the measured average lifetime.

Reliability Analysis of Pb-free BGAs Reballed with SnPb Solder
Author: Michael Meilunas

Abstract: Many component manufacturers now offer BGA packages only with Pb-free solder balls. This has led some assemblers to consider reballing the Pb-free devices with SnPb solder spheres in order to be used in a SnPb assembly process. Although the reballing process is relatively simple, the effects on the package, especially in terms of solder joint reliability must be addressed before the procedure can be implemented in a production process. This report describes an experiment in which SAC305 BGA packages were reballed with 63SnPb solder spheres, assembled to mother boards and subjected to thermal cycle testing in order to compare the reballed solder joints’ performance to non-reballed 63SnPb samples. Results were obtained for both ENIG and Cu OSP substrate finishes. The results indicate that the reball process reduces the reliability of the solder joint -in this case possibly due to increased voiding within the reballed solder joints, but the extent of the reduction may be acceptable for many applications.

Effects of Solder Ball Size on Accelerated Thermal Cycle Testing Results
Author: Michael Meilunas

Abstract: An accelerated thermal cycle experiment comparing similarly constructed BGA and CSP devices with SAC and SnPb solders was performed. Four package designs each containing 256 I/Os at 0.5, 0.8, 1.0 or 1.27mm pitch were subjected to three thermal cycle conditions in order to promote 2nd level solder fatigue. The test results were compared using Weibull analyses and scaling methods were applied to directly compare the performances of the packages. The results show that crack growth rate is highly influenced by the size of the solder ball and that thermal cycle dwell time is an important factor affecting the test results of the SAC305 solder.

Mixed Solder Alloy Reliability 2007
Author: Michael Meilunas

Abstract: Backward compatible soldering is a process in which Pb-free devices are assembled to PCBs using Sn/Pb paste resulting in “mixed” alloy solder joints. This report discusses the reliability of three backward compatible assemblies evaluated in 0/100oC thermal cycles with 10, 30 and 60 minute dwells and -40/125oC thermal cycles with 10 and 60 minute dwells. Results were compared to identical SAC305 samples assembled and tested in a similar manner. The findings strongly suggest that the mixed alloy stress relief process is not as sensitive to the thermal cycle test parameters as is SAC305.

Effects of PCB Pad Definitions on Drop Test Reliability
Author: Brian Roggeman

Abstract: Various pad definitions were studied in by both Joint Level testing and Board Level Drop to understand the effect on failure modes and failure rates. Traditional non-solder mask defined pads were compared to solder mask defined. Two separate assemblies were used that incorporated different component and pad sizes. The results indicated that changing the PCB pad to SMD prevents pad cratering but lifetime can either increase or decrease. The results illustrate that strength and fatigue scaling are not the same for different failure modes.

Investigation of Solder Joint Reliability under Various Bending Loads
Authors: Brian Roggeman and Michael Meilunas

Abstract: Mechanical bending loads, as a function of repeated key press for example, may eventually lead to solder joint failure. Current testing methodologies may not fully address the concerns. Electronic assemblies were subjected to 4-point bending to examine the behavior related to the different bending conditions, including variations in bending rates, bending amplitudes and directions of bend.

Pad Level Reliability of Via-in-Pad Structures
Authors: Brian Roggeman and Jing Li

Abstract: Pad failures, or cratering, are not necessarily limited to surface structures. Although via-in-pad structures are typically thought to be quite robust in terms of mechanical strength, cases have been presented which show cracking through or around the via. Evaluating their ultimate strength as well as resistance to repeated loading helps to identify potential issues related to design and/or materials. The robustness of blind via-in-pad structures is evaluated here using pad-level testing, with careful attention to failure modes and a comparison to similar surface pads.

Preconditioning of Pb-Free Solder Joints: Preliminary Results
Authors: Pushkraj Tumne and Brian Roggeman

Abstract: Reliability and qualification in the Pb free solder assemblies has always remained a critical issue during the design and development phase. It is imperative that tests developed to measure the reliability of the area array devices should conform with and simulate actual service conditions. In thermal cycling tests the solder joints undergo thermal as well as mechanical fatigue, but in order to decouple the effect of thermal and mechanical stresses for products such as hand held devices it is important to develop testing conditions which are similar to service conditions. For this purpose, preconditioning of solder joints has been studied to determine its effect on the mechanical integrity of the Pb free solder joints. Properties such as shear strength, fatigue resistance, and micro hardness have been measured at various times during the elevated aging process. It was found that there exists a distinct trend in change in the properties of the solder after elevated temperature aging, which hints to developing tests in the future with preconditioning as a protocol while screening the product.

Effect of Mechanical Preconditioning on Drop Test Failures
Author: Brian Roggeman

Abstract: Low level mechanical cyclic stressing was applied to PCB assemblies as a means to simulate everyday handling. Drop testing was then used to compare the preconditioned samples to non-conditioned samples. The reliability was found to be higher on the preconditioned samples. This suggests that low-level mechanical cycling may not induce significant damage, but rather it changes the mechanical behavior of the system. Micro-hardness testing was conducted on the solder joints and it was found that the joints soften with increased cycling.

Strain Behavior of Solder Joints During Thermal Cycling
Author: Brian Roggeman

Abstract: The thermal strains of actual solder joints were measured using in-plane Moiré Interferometry in an effort to better understand thermal cycling results. Both SnPb and SAC305 assemblies were used for comparative purposes. The strains in SnPb were found to be higher than SAC305. We also found that a post-cycled component had higher solder joint strain than a non-cycled component. The displacement behavior was also examined during an extended dwell at 100 °C to simulate the thermal cycling environment. SnPb showed continuing relaxation during the dwell, while SAC305 stopped relaxation after 30 minutes. The effects of this study suggest that, while there is primary creep in SAC solders, the secondary, or steady state creep is negligible, allowing us to simplify our thermal cycle prediction models.

Voiding in Lead-Free Paste Only Solder Deposits
Authors: Joseph W. Therriault, Emad Al-Momani, Pericles Kondos and Michael Meilunas

Abstract: The need to study the voids in paste only solder deposits, including the joints found in Micro Lead Frame and Quad Flat Land components, is evident, considering that voiding will in some cases affect both the thermal and electrical robustness of the joints. This study looked at the parameters affecting the percentage of voiding in small standoff (~2-3 mil) assemblies with Cu-OSP pads. Factors examined in this experiment predominantly included reflow profile characteristics and paste supplier. The results showed that some pastes even though specified as “low-voiding” fared no better with respect to area voided than did others without this characteristic. Reflow profile was a major factor influencing the voiding with a higher, longer soak and low peak profile generally showing the best performance. There were big differences from paste supplier to paste supplier, too. Based on these results, candidates were selected for the next phase of the planned reliability studies.

Thermal Cycle Parameter Evaluation Update
Author: Michael Meilunas

Abstract: This report is a companion piece to “2006 Pb-Free Update: Evaluating Accelerated Thermal Test Parameters for Select Solder Alloys”[1]. The report contains all the thermal cycle testing data from [1] plus additional data generated through December 2007. The experiment discussed in this report was designed to evaluate the reliability of four Pb-free solder alloys subjected to 0/100 and -40/125oC accelerated thermal cycles with 10, 30, 60 and/or 120 minute dwell times. The results indicate that the measured reliability of the Pb-free solders is highly dependent upon both dwell time and test temperatures.

Issues in Pb-Free Area Array Repair
Author: Laurence A. Harvilchuck

Abstract: Seemingly routine exercises in lead-free repair may become greatly complicated due to issues beyond the control of the operator or engineer. In this case, the component exhibited an inelastic deformation after each repair cycle. This deformation permitted an initial attachment of the component to the board in mass reflow, yet did not permit repair due to the cumulative warpage and ancillary factors causing bridging during subsequent reflow cycles. The small variations amongst these ancillary factors led to some reproducibility errors under otherwise identical process conditions.

Flip Chip Underfill Process Manual
Authors: Daniel Blass, Antonio Prats, Pericles Kondos and Peter Borgesen

Abstract: The capillary flow-driven flip chip underfill process may be taken to include the selection of equipment (dispenser) and encapsulant. Creation of the process certainly involves specification of parameters such as bakeout requirements, substrate temperature, dispensing pump, needle or nozzle size, dispense paths (height above the substrate, distance to chip edge, length of pass), dispense rate, needle or nozzle temperature, volume in each pass, timing of passes, and cure parameters. Optimization of the process and specification of the process windows should minimize important variations and account for the inevitable variations (statistics and tolerances). The present document offers a step-by-step approach to the development of the underfill process: Preparatory work, rapid process development for a given application, and troubleshooting. The individual sections of this document are organized to minimize the amount of experimental work actually required. The establishment of a sizeable knowledge base is strongly recommended, through work done by your materials and equipment suppliers, as well as by yourself during final qualification or the development of processes for individual applications. This knowledge base will be valuable in troubleshooting process problems.

Flip Chip Assembly Manual
Authors: Daniel Blass, Antonio Prats, Pericles Kondos and Peter Borgesen

Abstract: The following presents the framework for a comprehensive manual on the assembly of flip chips onto organic substrates. This manual is intended as a ‘living document’ which will continue to be updated as new knowledge is gained and should be viewed together with existing manuals focused on capillary underfilling of flip chip assemblies. At present flip chip assembly is often still exempt from RoHS, so this document addresses assembly of both eutectic Sn/Pb and no-Pb solders. In addition, it touches more briefly on adhesive and Au stud bumped based assembly.

Reflow Encapsulant/No-Flow Underfill Manual
Authors: Daniel Blass and Antonio Prats

Abstract: This is designed as a companion to the Underfill Process Codification. The aim is to present a guide to reflow encapsulant evaluation and process development. The focus here will be to highlight the differences, and to provide some simple and relatively quick characterizations that are necessary for reflow encapsulants. However, this should not be taken to mean that the establishment of a detailed and broad knowledge base is not important. The establishment of a sizeable knowledge base is strongly recommended, through work done by your materials and equipment suppliers, as well as by yourself during final qualification or the development of processes for individual applications. This document will also provide guidance for more detailed tests that will help with process development.

Component Underfill Manual
Authors: Daniel Blass and Antonio Prats

Abstract: BGAs and CSPs are typically reliable enough based on their design and optimized assembly processes and have not needed to be underfilled. Components, however, continue to either get larger or have smaller joints at the ball pitch decreases. For some applications, underfilling or other reinforcement will be required to ensure reliability of the BGA/CSP solder joints. Also helpful will be the information in our Flip Chip Underfill Process Manual. However, there are important differences between underfill for flip chip applications and underfill for packages. The present document offers an attempt at a step-by-step approach to the development of such processes: Preparatory work, rapid development of a process for a given application, and troubleshooting. The establishment of a sizeable knowledge base is strongly recommended, through work done by your materials and equipment suppliers, as well as by yourself during final qualification or the development of processes for individual applications.

Pad Cratering Test Methods and Specifications
Authors: Brian Roggeman and Jing Li

Abstract: The purpose of this document is to outline test methods for evaluating the mechanical strength and wear-out resistance of solder attachment pads. The method relies on applying a tensile force to the pad, using either mechanical clamping on a solder ball that has been pre-attached, or by pulling a wire that has been soldered to the pad. Initial specifications have been developed based on an extensive testing program to use as guidelines for evaluating laminates.

This is intended to be a “living document” and will be updated as new test results become available.

Area Array Rework Process Manual: Version 2007
Author: Laurence A. Harvilchuck

Revisions from 2006 to 2007:

1. Note on definitions of ‘repair’ and ‘repair’

2. Details regarding soldering scavenging with solder wick and a hot iron

3. Tools for repair of package-on-package (PoP) assemblies

4. Notes on pad cratering in area array repair

5. Package design and repair issues

6. Thermal profiling with various solder scavenging methods

Lead-Free Printed Circuit Board Process Manual: Version 2007
Author: Wayne T. Jones

Abstract: The transition to lead free soldering puts new demands on the laminate structures used, be they component substrates or printed circuit boards. In particular, there is great concern as to the potential for new or enhanced damage in assembly. Some of these concerns are obvious and testing or inspecting for them is straightforward, but others are much more subtle and/or may be very design, materials and component specific. Standard industry tests are found not to be very effective discriminators. Extensive research is ongoing to identify and characterize important damage mechanisms, and to define procedures to test for these, but meanwhile life must go on and practitioners continue to design and assemble new products.

The present document summarizes our current best recommendations for laminate materials selection and testing based on the results of our research results so far. This includes both our knowledge of specific materials and recommendations as to what else to test for, or have the supplier test for. Focus is on substrates and printed circuit boards constructed with multilayer lamination processes and common cost-effective material sets.

Comparison of Drop Reliability of SAC105 and SAC305 on OSP and ENIG Pads
Author: Brian Roggeman

Abstract: The selection of solder alloy and pad finish will affect drop/shock lifetimes. More compliant alloys are generally regarded as better performing in this type of loading condition, but the proper selection may depend on the pad finish used, as the failure mode is sometimes just as important as the failure rate. SAC105 and SAC305 alloys were tested on components with pad finishes of CuOSP and ENIG. We observed brittle failure modes for all test variables, and better lifetime with the SAC105 on Cu. On ENIG, we observed many early failures with SAC105 that suggests a difference in the intermetallic when compared to SAC305, which performed much more consistently.

Underfill Testing of Loctite 3536 Underfill with Pb-Free Solder Pastes
Author: Daniel Blass

Abstract: CSP components were built with three Pb-free SAC305 solder pastes and underfilled with Loctite. The underfill layer was examined for defects, such as voiding or cracking. Flat-sections were made that removed either the component or the PCB. There were few shrinkage voids and no shrinkage cracks. Most of the voids observed formed in the solder mask openings around the PCB pads.

Underfill Testing of Emerson & Cuming E1161 with Pb-Free Solder Pastes
Author: Daniel Blass

Abstract: CSP components were built with five Pb-free SAC305 solder pastes and underfilled with Emerson & Cuming E1161. The underfill layer was examined for defects, such as voiding or cracking. Flat-sections were made that removed either the component or the PCB. Many voids were found around the solder joints with each solder paste. The voids tended to be closer to the PCB side of the solder joints. Considering the modulus and Tg of this underfill, these voids are a reliability concern for thermal cycling and other thermal excursions, such as rework of a nearby part. The voids should not affect mechanical robustness, such as drop test performance.

Whiskering on a NiAu Lead Soldered with SnAg Solder
Author: Daniel Blass

Abstract: This report characterizes whiskering on the leads of a 0.5mm pitch surface mounted board to board connector. The leads are NiAu plated Cu. SnAg solder was used to attach the connector the ENIG finished PCB pads. Whisker testing would not normally be performed on a NiAu finished part but whiskers were found on the solder coated connector leads after long term storage at 60°C/87%R.H. Small eruptions and short, thick, striated filaments were most common. There were a smaller number of thin, long filament whiskers. Two whiskers were nearly 150 microns (6 mils) long.

The solder on the top and sides of the lead was found to be 2-3 microns thick with much of this thickness being intermetallic compounds. Some of the intermetallics were Au-rich plating on the leads. Printing more solder paste would produce a thicker layer of solder on the Ni lead surface that should be less likely to whisker. The thick Au plating on the connector lead may play a role but it facilitates electrical contact between the plug and receptacle.

Reliability Results for SAC305-Bumped Flip Chips in Several Thermal Cycles
Author: Daniel Blass

Abstract: SAC305-bumped flip chip assemblies were built on thin organic substrates and encapsulated with 8 underfills. The mechanical properties of the underfills varied. Assemblies were tested in three liquid shock conditions and one air thermal cycle. Two high CTE underfills gave early failure but the one with a Tg below the dwell temperature failed 3.5 to 6 times faster. Lower CTE underfills with Tg near or slightly below the dwell temperature did very well in 5 and 15 minute dwell liquid shock tests. Changing to a long dwell air to air cycle gave failure in about 25-40% as many cycles compared to the shock tests. Two higher Tg underfills with lower CTEs were tested but the failure mode was corner fillet cracking and corner delamination rather than solder joint fatigue.

Crack Growth Analysis of SAC305 Solder Subjected to -40/125oC Thermal Cycling
Author: Michael Meilunas

Abstract: The crack growth rate of three similarly constructed SAC305 BGAs subjected to -40/125oC thermal cycling with 10 minute dwell times was calculated using a dye penetration measurement technique. The results for all three packages were compared to the measured lifetime of comparable components in the same thermal cycle. The experiment shows that a.) crack growth rate is relatively constant after some initial cycling and b.) the computed average crack growth rate using the dye penetration method, if used to predict the reliability of a population, would produce an average lifetime significantly greater than the measured average lifetime.

Backward Compatible Fine Pitch CSP Build and Thermal Cycling With and Without Underfill
Authors: Daniel Blass and Michael Meilunas

Abstract: A variety of 0.4 and 0.5mm pitch CSPs were built with a SnPb solder paste. Component ball alloy was either eutectic SnPb or Pb-free (SAC305 or SAC405). Both SnPb and Pb-free versions of several components were assembled while the remaining components were available in either SnPb or SAC. The six layer PCB measured roughly 14” x 17” and was 2mm thick and had a Cu-OSP pad finish. Some of the components were underfilled with Emerson and Cuming E1159 reworkable CSP underfill. Unlike most reworkable CSP underfills, the glass transition temperature (Tg) is relatively high at 105°C and the storage modulus is 2.7GPa. Thermal cycling was conducted with 15 minute dwells at 0°C and 100°C. The results prove that the selected underfill can significantly improve the reliability of the SnPb assemblies tested, but significantly reduces the reliability of the mixed solder (SnPb + SAC) assemblies tested.

QFN Process Board 2007 Design Overview
Author: Michael Meilunas

Abstract: “QFN Process Board 2007” is a 1.0mm thick, 8 layer printed circuit board designed for evaluating surface mount assembly processes, thermal cycle reliability and drop test reliability with Quad Flat No Lead and similar leadless devices. 120 test boards were acquired for such purposes in late 2007. The following report describes the basic test board construction and design details.

Test Board 2007 Design Overview
Author: Michael Meilunas

Abstract: “BGA/QFN Test Board 2007” is a 12 layer printed circuit board designed with input from several Consortium members. The board’s primary function is to serve as the motherboard for several large I/O surface mount devices which will be subjected to accelerated thermal cycle testing. The board serves a secondary function for quad flat no-lead PCB land design evaluations and thermal cycle testing. The following paper describes the test board features, materials and construction.

Comparison of PCB Pad Definitions on Drop Test Reliability
Author: Brian Roggeman

Abstract: Various pad definitions were studied in by both Joint Level testing and Board Level Drop to understand the effect on failure modes and failure rates. Traditional non-solder mask defined pads were compared to solder mask defined. Two separate assemblies were used that incorporated different component and pad sizes. The results indicated that changing the PCB pad to SMD prevents pad cratering but lifetime can either increase or decrease. The results illustrate that strength and fatigue scaling are not the same for different failure modes.

Brittle Failures of Joints on Electrolytic Ni/Au
Authors: Pericles A. Kondos, Pushkraj Tumne and Joseph W. Therriault

Abstract: Experiments were conducted on SAC, SnAg and SnPb solder spheres attached to electrolytic Ni/Au pads. Some of the resulting bumps had Cu added to them in a second reflow, to simulate assembly on Cu PCB’s. The bumps were subjected to pull tests under conditions that caused many of them to fail with brittle failures in the intermetallic region. The intermetallic strength distributions were extracted from the data with the Kaplan-Meier method. The failure surfaces and the intermetallic microstructure and composition were studied in detail. It was seen that the addition of Cu to formerly Cu-free bumps significantly reduced intermetallic strength, making them quite weaker than bumps that had started as SAC, which changed little after the addition of more Cu. None of the bumps in these experiments became extremely weak, but some “missing balls” might have been seen in tests too recent to be included here.

Investigations of Brittle Failure of IMCs on ENIG
Authors: Pericles A. Kondos, Joseph W. Therriault, Pushkraj Tumne and Jing Li

Abstract: Several aspects of brittle failures of intermetallics on ENIG substrates were examined last year. A consortium member reported a problem with early failures of ENIG components from a particular batch assembled on Cu-based boards. Tests with unassembled components were performed in APL to determine if problematic components could have been detected before assembly. These tests included ball pull tests before and after the addition of Cu dust in the solder, SEM analysis of failure surfaces, and microstructure studies of cross-sectioned components. The “good” batch was then compared with other substrates to see if it was as good as ENIG could be. The assumption that intermetallic strength can be scaled with the pad area was tested. Other ENIG issues examined were the effect of solder composition on intermetallic strength and the question of “delayed” black pad – specifically, if it can be explained by a possible weakening of the intermetallics due to the thermal aging effect of thermal cycling.

Toward a Better Understanding of the Cause of Voiding in Cu3Sn
Author: Liang Yin

Abstract: Previous consortium studies have indicated that the root cause of voiding in Cu3Sn is resulted from impurity incorporation during Cu electroplating. The level of impurity incorporation was observed to depend greatly on plating additive chemistry and process parameters. The present report first reviews the results from plating solutions with generic organic additives, in terms of the effects of additive combination, current density, bath temperature, and bath age. Based on the parabolic adsorption behavior typically seen for organic molecules in aqueous plating solutions, a hypothesis is proposed to correlate impurity incorporation with the crystallographic surface orientation of electroplated Cu. The hypothesis is supported by the results of XRD (x-ray diffraction) texture analysis. The experimentally observed dependences of voiding propensity on additive chemistry and process parameters are well described by the hypothesis.

Voiding Propensity of Commercial Cu Plating Additive Systems
Authors: Liang Yin and Mao Gao

Abstract: Voids have been occasionally found in the Cu3Sn intermetallic compound after thermal aging of solder joints made on Cu-pads. Previous investigations have indicated that the root cause of the voiding phenomenon is associated with the incorporation of certain organic/inorganic impurities during Cu electroplating. In this study, propensity for voiding of samples plated from four commercial Cu plating additive systems were surveyed and compared. The voiding propensity was seen to be greatly dependent on the additive chemistry and bath age. Periodic bath purification process of carbon treatment appeared to be effective to reduce voiding propensity. Effects of photo resist leaching, rectification and electrical current waveform on voiding level were also evaluated.

Additives for Cu Electroplating and Voiding in Cu3Sn
Author: Liang Yin

Abstract: The sporadic voiding in the Cu3Sn intermetallic compound (IMC) formed in solder/Cu pad interconnects is believed to be related to impurity incorporation during Cu electroplating. The present report focuses on the effect of plating additives chemistry on the propensity for voiding. Chloride ions (Cl-) and two generic organic additives, suppressor poly-ethylene glycol (PEG) and accelerator bis-(3-sulfopropyl)-disulfide (SPS), were selected for investigation at a constant current density of 10 mA/cm2. Cu samples were plated by using a rotating disk electrode (RDE) apparatus from ten additive combinations. For non-SPS containing additive combinations, voiding level remained low except when Cl- and PEG were added together. For SPS containing combinations, voiding level was greatly reduced when all three additives were present. Discussions on additive interactions, adsorption and their effects on voiding propensity are presented.

Effect of Plating Bath Temperature on Voiding in Cu3Sn
Author: Liang Yin

Abstract: Previous study has indicated that the voiding propensity of electroplated Cu depended on current density, whose variation also led to overpoential change. In order to evaluate the effects of current density and overpotential independently, two generic plating additive systems were investigated at a constant current density with various plating bath temperature. One system contained poly-ethylene glycol (PEG) and chloride ions (Cl-), and the other one contained bis-(3-sulfopropyl) disulfide (SPS), PEG and Cl-. Overpotential was observed to decrease with temperature for both systems, however voiding behavior exhibited opposite trends with temperature. It appears that overpotential is the primary variable for the voiding propensity for a given bath chemistry.

Effect of Plating Current Density on Voiding in Cu3Sn
Author: Liang Yin

Abstract: Organic impurity incorporation during Cu electroplating is believed to be the root cause for the sporadic voiding phenomenon occurring in Cu3Sn intermetallic compound (IMC). The present report addresses the effect of plating current density on the propensity for voiding. Two generic plating additive systems were evaluated. One contained poly-ethylene glycol (PEG) and chloride ions (Cl-), and the other one contained bis-(3-sulfopropyl) disulfide (SPS), PEG and Cl- . Cu samples were plated using a rotating disk electrode (RDE) apparatus at various current densities. Quantitative analysis of impurity level was conducted by secondary ion mass spectrometry (SIMS). In the current density range of 0.5-40 mA/cm2, voiding level was observed to increase with current density for the PEG+Cl- system. However, SPS+PEG+Cl- exhibited an opposite trend. The measured impurity levels correlated well with the voiding level seen afterwards.

Effect of Bath Age on Voiding in Cu3Sn
Author: Liang Yin

Abstract: Previous studies have shown that the voiding propensity of electroplated Cu depended on additive chemistry and plating parameters, i.e. current density and bath temperature. In present study, the effect of plating bath age was investigated for a generic additive system composed of chloride ions and two organic additives: bis-(3-sulfopropyl) disulfide (SPS) and poly-ethylene glycol (PEG). Samples were plated sequentially at 10 mA/cm2. Potential evolution, surface morphology and voiding behavior of plated samples were studied and compared. In the first 5 hours of plating, the bath appeared to be stable. Further plating was accompanied by noticeable changes of potential evolution and surface morphology, but the voiding level remained low. After 18 hours, the bath behaved the same as a PEG+Cl- additive system.

Shadow-Moire Study of Flip Chip Underfill Relaxation in Simulated Thermal Cycles
Authors: Brian Roggeman and Daniel Blass

Abstract: Warpage of flip chip assemblies built with 8 underfills was studied in simulated thermal cycles. The mechanical properties of the underfills varied and the Tgs ranged from 90°C to 145°C. An AkroMetrix TherMoiré® system was used to measure warpage. The assemblies were heated from room temperature to a dwell at 100°C or 125°C. With a ramp rate of 27°C/min, the chip warpage did not change after reaching a 100°C dwell except for the lowest Tg (90°C) underfill. With the same ramp to a 125°C dwell, the lowest Tg underfill reached minimum warpage at the beginning of the dwell. Most of the other underfills relaxed for several minutes during the dwell before reaching minimum warpage. An underfill with a 124°C Tg took the longest time, as much as 10 minutes, to reach minimum warpage at 125°C. Warpage was also measured with a slower 10°C/min ramp rate to a 100°C dwell. Warpage did not change after reaching a 100°C for any of the underfills.