AREA CONSORTIUM REPORTS

Assembly Of Flip Chip Csps And Leadless Csps On Test Board-6
Authors: Muffadal Mukadam and K. Srihari

Abstract: This report summarizes the results of an assembly experiment that was performed at Universal Instruments Corporation. This assembly experiment, which consisted of six different build matrices, addressed two separate studies. The first study was the assembly of Flip Chip Chip Scale Packages (FCCSPs) with different package constructions using eutectic (63Sn/37Pb) solder, and second, the lead-free (95.5Sn/3.8Ag/0.7Cu) assembly of four leadless CSPs.

The first study concentrated on the assembly of four FCCSPs having 124 I/Os and 0.5 mm pitch. These were selected so as to measure the effects of package body size, component pad design (circular vs. spoked), and second level interconnection (solder bumped vs. leadless), along with interaction between these factors. The purpose of the second study was to compare the four leadless CSPs using lead-free solder paste. Moreover, each of these leadless CSPs were assembled on four sub sites with varying board pad sizes. It would also be possible to compare leadless CSPs assembled using Sn/37Pb and lead-free solder pastes.

The builds also incorporated additional surface mount components such as Ball Grid Arrays (BGAs) and chip resistors. The assemblies were performed on mulitlayered FR-4 Printed Circuit Boards (PCBs). The assembly build matrices, the PCBs for assembly, the various components, the solder pastes, and the assembly parameters are discussed in this report.

The assemblies were electrically tested for daisy chain continuity to determine the defect levels for each component. The assemblies were then inspected using X-ray imaging to detect the presence of solder joint defects and voiding. Solder joint formation, wetting around the attachment pads, and solder joint collapse were investigated through cross-sectional microscopy. There were no differences observed in the assembly of the different FCCSPs. Solder joint voiding was primarily observed in the assemblies of the leadless CSPs due to their low standoff.

Some of the defects that were observed in this characterization study include solder joint bridging, incorrect component orientation, and component related defects. Based on the observed defect levels, the assembly yield for each component type was projected. The results of the characterization study are summarized in this report.

Csp Assembly Build At Manufacturers’ Services Limited (Msl)
Authors: Ursula Marquez and K. Srihari

Abstract: The primary goal of this project was the implementation of a “robust” CSP assembly process in a contract manufacturing environment. Four types of CSPs were assembled onto organic Printed Circuit Boards. The assembly process, including stencil printing process, component placement, and reflow soldering, was optimized through experimentation. The assemblies were characterized through x-ray analysis, cross-sectional analysis, and electrical testing. A total of 12 boards were assembled. No “time-zero” failures were observed in any of the assemblies. All the components exhibited good solder joint formation on both Electroless Nickel Immersion Gold (ENIG) and Copper Organic Solderability Protection (Cu-OSP) coated Printed Circuit Board pads. X-ray analysis of the assemblies showed no cases of solder bridging, misregistration, or opens.

Chip Scale Package Polyimide Flex Test Board #9
Author: Anthony A. Primavera

Abstract: Chip Scale Package Test Board #9 (CSPTB-9) is designed for the assembly and reliability analysis of several types of surface mount and area array components. CSPTB-9 utilizes polyimide non-reinforced dielectric layers as the base material and was produced in both 4 layer and 6 layer formats. Test structures for evaluation of microvias were incorporated in both designs. Several test variables were designed into the via chain test region of the board including; via diameter, capture pad dimensions, blind and buried structures, and inner layer capture pad designs.

This report presents an overview of the design specifications of CSPTB-9 such as pad dimensions, solder mask dimensions, component characteristics, and descriptions of the various test sites on CSPTB-9. The Printed Circuit Board (PCB) stack-up and the details of the constructional materials of the test board are presented in this report. The attachment pad dimensions and pitch, the thickness of the test vehicles, and the solder mask dimensions and registration were characterized in this study.

In addition to PCB characterization, test boards were assembled in both single and double side configurations. This report details the assembly parameters utilized in this experiment and presents the results of post assembly inspection. A total of 60 circuit boards were assembled in this study, of which 30 were the 4 layer design and 30 were the 6 layer construction. Several assembly variables were evaluated in this study including; component construction, single versus double sided, and board layer count. A comparison of land grid array (LGA) and ball grid array (BGA) formats was made possible by use of similar components with and without solder bumps. In addition, evaluation of packages with stacked multiple silicon die were performed in this study. A total of 8 builds cells were performed with 10 PCB being assembled in each cell. However, 2 of the cells were double side assembles which utilized board from other cells. This resulted in the assembly of 60 unique PCBs rather than 80 boards. The build cells included 2 single side builds for each board construction (4 versus 6 layer), and 1 build for each thickness board in double side fashion.

A variety of board, component, and assembly related issues were discovered during this build, which are presented in this report. Post assembly defect analysis was performed for each type of defect. A complete evaluation of the post assembly solder joint quality and defect rate is presented in this report.

Reflow Encapsulants For Csp Underfilling – Assembly And Reliability Issues
Authors: Murtuza Rampurawala and K. Srihari

Abstract: An alternative to capillary flow underfills is reflow encapsulants, also called flux-filled or no-flow encapsulants. When reflow encapsulants are used to underfill CSPs, the underfill material is dispensed before the assembly of the component. The underfill also provides the fluxing action to form the solder interconnection between the device and the Printed Circuit Board (PCB). The use of reflow encapsulants in place of capillary flow underfills increases throughput as it decreases the number of process steps.

Three different Chip Scale Package (CSP) devices were assembled onto multilayered test boards using two different reflow encapsulants. The underfilled CSP assemblies were characterized through visual inspection, fillet thickness measurements, x-ray analysis, and cross-sectional microscopy to study the fillet formation, underfill flow beneath the package, and solder joint formation. The assemblies were subjected to torsion testing and the results were compared to those of non-underfilled assemblies. The failures were analyzed using cross-sectional microscopy. An increase of 10X to 13X in torsion cycling reliability was obtained for the underfilled samples when compared to non-underfilled samples. Thermal cycling tests are presented in a separate report.

Partial Underfilling Using The Four-Corner Attach Process
Authors: Murtuza Rampurawala and K. Srihari

Abstract: Chip Scale Packages (CSPs) in portable electronic applications require a higher mechanical reliability due to the high mechanical stresses of drop and shock compared to CSPs used in desktop applications. Underfilling CSPs provides a significant increase in the mechanical strength of the assembly, which improves resistance to stresses that are induced due to impact, torsion, and vibration.

Typically, a capillary flow underfill process is used to underfill the entire CSP package, which increases assembly process time significantly. A proposed alternative approach which utilizes dispensing underfill droplets only at the four-corners of the component was evaluated in this study. If proven successful, partial underfilling process would be ideal for applications where an increase in the mechanical shock resistance is a primary concern, and time cannot be allotted for a complete underfill process. In the partial dispense process, underfill was dispensed only at each corner of the package body, which resulted in a process time that was 50% less than a full underfill of the same device.

Reliability studies were performed using accelerated test conditions to compare CSPs assembled with no underfill, traditional full underfill and samples underfilled at the corners only. The packages were subjected to a cyclic torsion test at 3.0 degrees of deflection. An increase in reliability of approximately 1.5X to 2.0X was observed in partially underfilled Package Z (0.8 mm) pitch and Package AH (0.8 mm) pitch assemblies as compared to non-underfilled assemblies. A significant reduction of approximately 50 to 60% in the time to underfill was obtained for the partially underfilled samples when compared to fully underfilled samples.

Process Development And Mechanical Testing Of Csp Underfills
Authors: Murtuza Rampurawala and K. Srihari

Abstract: Chip Scale Packages (CSPs) are widely used in portable devices. They offer robust interconnects and higher standoffs in comparison to flip chips. CSPs in portable devices pose new reliability requirements due to the high mechanical stresses experienced during their service lifetime. The stresses are primarily generated due to impact, shock, vibration, mechanical bending, and thermally induced fatigue due to the CTE (Coefficient of Thermal Expansion) mismatch between the CSP and the Printed Circuit Board (PCB). These stresses can be greatly reduced by using an underfill material between the CSP and the PCB.

In this study, five distinct underfill materials were studied using six CSP package designs. The CSPs used for this study represent a range of components with different dimensions, construction, materials, etc. Various underfill dispensing patterns were studied. Initial analysis indicates that underfills may trap voids in high I/O fine pitch, perimeter arrays.

This study was aimed at evaluating the effect of underfill on the mechanical reliability of CSPs. Four of the five underfills tested performed satisfactorily when subjected to JEDEC (level 3) moisture / reflow preconditioning testing. Initial analysis shows that underfilled packages survive about 2–3 times longer than non-underfilled packages in torsion testing. None of the underfilled samples failed in vibration testing, while failures were recorded in non-underfilled samples.

Test Board 7 Ball Grid Array Build
Author: Michael Meilunas

Abstract: Universal Instruments’ Consortium Test Board 7 side C (TB7-C) was designed to evaluate assembly and reliability issues associated with daisy-chained 1.27mm pitch, 256 I/O ball grid array (BGA) devices. 30 immersion gold over electroless nickel (ENIG) and 24 copper OSP TB7-Cs were assembled in Mid 2002 with five BGA designs and three solder alloys, including lead-free formulations.

The following report describes the test board design, component construction, and solder alloys pertinent to the builds. Assembly details including printer information, pick and place operations and reflow profiles are included. Post-assembly inspection and analysis may also be found in this report as well as a brief description of the tests that are to be performed on the TB7-C BGA assemblies.

Fluxing Techniques For Wafer Level Csp Assembly
Authors: David Esler and K. Srihari

Abstract: Wafer Level Chip Scale Packages (WLCSPs) are bridging the gap between flip chips and Chip Scale Packages (CSPs) in terms of pitch and ball size. Roadmaps for WLCSPs indicate widespread use of sub 0.5 mm pitch WLCSPs in the near future. Integrated flux assembly processes, similar to those used in flip chip assembly, need to be developed for WLCSPs to reduce the defects typically seen when fine pitch components are assembled using solder paste printing. Three fluxing techniques for WLCSP assembly, thin film application, dispensing, and jetting were evaluated in this research. Within a GSM placement machine, a Universal GSM Thin Film Applicator (TFA) unit was used to flux and place components. In addition, the two stand-alone automated fluxing units, an Asymtek DJ-2200 (for flux jetting) and a Creative Automation Champion 3700 (for flux dispensing), were evaluated in this study. The three fluxing techniques were evaluated based on their ability to form robust and reliable solder joints. Relative comparisons between each fluxing technique were also drawn.

Two types of solder (eutectic Sn/Pb) bumped WLCSPs were considered in this study. These devices were assembled on multi-layered test boards utilizing all three fluxing techniques. The resulting solder joints were studied using cross-sectional microscopy and X-ray analysis to investigate solder bump collapse and wetting of the solder to the pads on the test boards. The WLCSP assemblies were tested for electrical continuity to determine the electrical connection between the WLCSP and the Printed Circuit Board (PCB). The WLCSP assemblies were also subjected to thermal cycling reliability testing. This report presents the process issues with each fluxing technique, the results of the characterization study of the WLCSP assemblies, and the thermal cycling reliability testing.

“Underfilling Of Wafer Level Csps Using Capillary, Partial, And No-Flow Underfills”
Authors: Murtuza Rampurawala and K. Srihari

Abstract: Chip Scale Packages (CSPs) that are used in portable electronic devices, such as cellular phones, are required to operate in relatively harsh “mechanical” working conditions. New reliability issues caused by static loading, bending, twisting, and impact shock have to be addressed. Underfilling CSPs provides adhesion between the CSP body and the motherboard. Bending forces that occur during impact or vibration are distributed over the entire array of solder bumps and the underfill material. This approach of reinforcing a CSP assembly improves its mechanical reliability [Yaeger, 2001].

Three different wafer level CSP devices were assembled onto multilayered test boards using a flux-only assembly process, followed by an underfill step using a capillary flow material. In addition, component were partially underfilled using a high viscosity corner bond material. A third approach utilizing a flux-encapsulant was utilized in this experiment as well. In this process, the material is dispensed prior to chip placement which combines the flux and underfill steps. The process steps taken to assemble and underfill the various wafer scale components are discussed in this report. The underfilled CSP assemblies were characterized through visual inspection, fillet thickness measurements, x-ray analysis, cross-sectional microscopy, and C-mode scanning acoustic microscopy (CSAM) to study the fillet formation, underfill flow beneath the package, and solder joint formation. Several time-zero failures were observed in assemblies underfilled using reflow encapsulants due to premature gellation of the reflow encapsulant when using a reflow profile with a long time to peak temperature (256 seconds). No failures were observed when a short duration profile (less than 190 seconds to peak) was used for the same reflow encapsulant. The failures were analyzed using cross-sectional microscopy and Scanning Electron Microscopy (SEM) analysis, the results of which are presented in this report.

Overview Of Test Structures Designed On Csptb-7
Authors: Ursula Marquez, Hendra Hartono, David Esler and K. Srihari

Abstract: Chip Scale Package Test Board – 7 (CSPTB-7) is a multilayered high density Printed Circuit Board (PCB) with two signal layers and two ground layers. CSPTB-7 is designed to study the assembly and reliability of Chip Scale Packages (CSPs), Ball Grid Arrays (BGAs) (up to 1517 I/Os), Quad Flat Packs (QFPs), and leadless CSPs. In addition, it is designed to study a variety of active components such as Subscriber Identity Module (SIM) connectors, Small Outline Packages (SOPs), Thin Small Outline Packages (TSOPs), Thin Shrink Small Outline Packages (TSSOPs), Small Outline Transistors (SOTs) and passive components. Beside these test structures, CSPTB-7 contains test sites for wetting studies of solder paste/spheres on different surface finishes and for the evaluation of shear strength of solder joints.

This report presents an overview of the design specifications such as pad dimensions, solder mask dimensions, component characteristics, and descriptions of the various test sites on CSPTB-7. The pad diameter, the solder mask openings, and the stencil apertures for side F of CSPTB-7 were measured, the summary of which is presented in this report. One board and 30 measurements per sites (6 sites) were considered. In most cases, the dimensions of the pads and the solder mask openings were smaller than the design specifications. On the other hand, the stencil aperture dimensions were larger than the design values.

Chip Scale Package Test Board #8 Part A (Csptb-8a) Design Of Test Structures
Authors: Arun Gowda, Ken Tojima and K. Srihari

Abstract: Chip Scale Package Test Board #8 part A (CSPTB-8A) is designed for the assembly and reliability analysis of a 52.5 mm, 2577 I/O, 1.0 mm pitch flip chip ball grid array device (Package BV). Package BV is a high-performance device that is typically utilized in hi-end information systems and communications applications. CSPTB-8A was designed to be 93 mils thick. The test board has 14 copper layers and utilizes plated through-holes for interconnection between the signal/ground layers. CSPTB-8A also has assembly sites for two 0.75 mm pitch Chip Scale Packages (CSPs) to validate the assembly process that is developed for Package BV. CSPTB-8A was obtained with immersion silver and electroless nickel/ immersion gold surface finishes.

This report presents an overview of the design specifications of CSPTB-8A such as pad dimensions, solder mask dimensions, component characteristics, and descriptions of the various test sites on CSPTB-8A. The Printed Circuit Board (PCB) stack-up and the details of the constructional materials of the test board are presented in this report. The attachment pad dimensions and pitch, the thickness of the test vehicles, and the solder mask dimensions and registration were characterized in this study.

Chip Scale Package Test Board #8 Part B (Csptb-8b) Design Of Test Structures
Author: Arun Gowda

Abstract: Chip Scale Package Test Board # 8 revision B (CSPTB-8B) is a multi-layered, high density Printed Circuit Board (PCB). CSPTB-8B is designed to study assembly and reliability issues related to advanced component technologies. The test board includes sites designed for Chip Scale Packages (CSPs), Ball Grid Arrays (BGAs), leadless CSPs, wafer level CSPs, and BGA connectors.

This report presents an overview of the CSPTB-8B design specifications such as pad dimensions, solder mask dimensions, and descriptions of the various test sites found on the board. Stack-up configuration and construction materials are discussed.

This report also includes a brief description of the various packages that may be assembled to CSPTB-8B.

Test Board 7-E/F Build
Author: Michael Meilunas

Abstract: Universal Instruments’ Consortium Test Board 7 panel E/F was designed to evaluate assembly and reliability issues associated with daisy chained 1.0mm pitch BGA devices, 0.5mm pitch TQFNs, 0.8mm pitch LGAs, 0.5mm pitch ETCSPs, and 0.8mm pitch CSPs. An assembly build was performed in November 2002 using 14 immersion gold over electroless nickel and 12 copper OSP Test Board 7 panel E/Fs. Paste was deposited over the test boards through a stencil printing process, components were placed with a GSM and the assemblies were reflowed in a forced convection reflow oven.

The following report includes the test board design and component construction. Assembly details including printer information, pick and place operations and reflow profiles are included. Post-assembly inspection and analysis may also be found in this report.

Assembly Build And Characterization Of Test Board 7-Side F
Authors: Hendra Hartono and K. Srihari

Abstract: Test Board 7-side F is a multilayered test vehicle with sites for the assembly of stacked Chip Scale Packages (CSPs) and thin profile Ball Grid Arrays (BGAs). This report discusses the assembly process and issues related with the assembly of these area array devices on different pad sizes and surface finishes.

Packages BD and DE (stacked CSPs) and Package BH (extremely thin profile BGA) were assembled on Test Board 7-side F (TB7-F) using no-clean, eutectic Sn/Pb, Type 4 solder paste. The assemblies were characterized through electrical testing, x-ray, and cross-sectional analysis to inspect the integrity of the solder joints. The cause of assembly defects was also investigated.

Two time-zero failures were observed on Package BH due to incomplete developed solder masks on several pads at site F1 and F3. One cross-section shows that the solder mask completely covered the pad surface. Other cross-section shows that the solder mask partly covered the pad surface. Package BD and BE show that no time-zero failure. All of these packages pass the electrical testing.

Effect Of Aging – An Update To The Reliability Module
Authors: Ramasamy Muthaiyan and K. Srihari

Abstract: The characteristic life of a component assembly and the factors that affect it are of significant concern in the area array domain. Numerous reliability experiments have been performed through the Area Array Consortium at Universal Instruments Corporation. The results of these experiments show that the solder joints of some area array devices, when subjected to elevated temperatures for an extended period of time, transform from a ductile solder fatigue failure to an interfacial separation at the solder to nickel pad. This issue is predominant in the case of area array packages using the electroless nickel / immersion gold metallurgical system. The root cause of this problem is attributed to the formation of a ‘Sn-Ni-Au’ intermetallic layer that forms during exposure to high temperatures.

This report describes the ‘Aging Module’, which can assess the time (number of cycles) at which a transformation from fatigue to interfacial failures occurs in a solder joint. The ‘Aging Module’ is based on the Arrhenius rate equation and was developed using Microsoft Visual C++. After validating and testing the performance of the ‘Aging Module’, it was incorporated into the ‘Reliability Module’ of the ‘Codification Software’. This utility update in the ‘Reliability Module’ would help the user in predicting the number of cycles (air-to-air thermal cycling) at which the solder joints of an area array component undergo a fatigue to interfacial failure transformation. Consequently, the failure mode (fatigue / interfacial embrittlement) of the area array component can also be assessed.

Router Advisor
Authors: Ramasamy Muthaiyan and K. Srihari

Abstract: Area array surface mount components offer many potential advantages such as efficient board real estate usage, wide assembly process window, high yield and reliability, and better electrical performance, when compared to traditional fine pitch components. However, the high density of I/Os in area array surface mount components increases the substrate design complexity significantly. To address the routing of area array components on Printed Circuit Boards (PCBs), a ‘Router Advisor’ was designed and developed. The ‘Router Advisor’ effectively and efficiently assists the user in designing a substrate for area array components.

The ‘Router Advisor’ is a software tool that provides the framework for a decision support system. This module incorporates basic rules for designing a substrate. The user friendly ‘Router Advisor’ was designed and programmed using Microsoft Visual Basic 6.0. A large body of information (component characteristics and board manufacturer’s specifications) is stored using Microsoft Access 97, which serves as the database. This module has context sensitive help files, which can be accessed even during the execution of the program.

This report provides ‘step-by-step’ instructions on how various features of the ‘Router Advisor’ can be used and enables the user to fully explore the features of the software.

Updates To The Codification Software
Authors: Ramasamy Muthaiyan and K. Srihari

Abstract: The ‘Codification Software’ is a decision support / expert system, which serves as a guide (knowledge base) for process and design engineers in the electronics manufacturing industry. It was developed within the Area Array Consortium at Universal Instruments Corporation, Binghamton. At present, the ‘Codification Software’ consists of a suite of modular applications such as the ‘Component Browser’, ‘Warpage Module’, ‘Reliability Predictor’, and ‘Router Advisor’. The ‘Codification Software’ aids the user in:

1. Correlating component characteristics and experimental conditions (assembly parameters and thermal testing conditions) with reliability data;

2. Data / sensitivity analysis;

3. Decision making; and

4. Predicting results (cycles to fail, warpage of a substrate, and printed circuit board routing).

The life cycle of the ‘Codification Software’ is similar to that prescribed by Software Development Life Cycle (SDLC) theory. This report elaborates the operational changes (updates / modifications) that were performed on the applications in the ‘Codification Software’.

“Characterization Of Bgas, Wafer Level Csps, And Micro Leadframe Devices”
Authors: Shafi Saiyed and K. Srihari

Abstract: This report contains the dimensional characterization of several area array devices that were recently evaluated through Air-to-Air Thermal Cycling (AATC). The external dimensions of the devices including the pitch, the body dimensions, and package height were measured using a Coordinate Measuring Machine (CMM). The internal construction of the devices was studied using cross-sectional analysis and a metallograph. The die size, the chip carrier thickness, the overmold dimensions, and the solder bump dimensions were some of the internal dimensions that were measured. This report summarizes the dimensional characterization of fourteen area array devices that included Ball Grid Array (BGA) packages, Chip Scale Packages (CSPs), Wafer Level CSPs (WLCSPs), and micro leadframe devices.

Characterization Of Wafer Scale And Elastomeric Based Csps

Authors: Murtuza Rampurawala and K. Srihari

Abstract: There has been a constant drive in the electronics industry towards high-performance and miniature products. These advances have led to many new Integrated circuit (IC) technologies. Drivers such as size, speed, weight, performance and cost are making Chip Scale Packages (CSPs) an important element in the packaging industry. This report presents the characteristics of several different wafer level and elastomeric CSPs.

The CSPs were characterized through cross-sectional analysis, moisture absorption/desorption and moisture sensitivity studies, warpage, and Coefficient of Thermal Expansion (CTE) measurements. Moisture sensitivity studies were performed at lead-free reflow temperatures to study the effect of high reflow temperatures (260°C) on the integrity of the packages. The warpage and CTE measurements were obtained by Shadow Moiré analysis.

A package overview that includes the internal construction, external dimensions, and manufacturing processes is presented. In addition, results and inferences from the moisture sensitivity studies, the warpage and CTE measurements are presented in this report.

Characterization Of The Mixed Assembly Build On Csptb6
Authors: Hendra Hartono, Shiva Kalyan Mandepudi, David Esler and Murtuza Rampurawala

Abstract: This report discusses process issues that relate to the assembly of different component technologies, including wafer level Chip Scale Packages (CSPs), flip chip CSPs, chip capacitors, chip resistors, and Through-Hole Components (THCs). The component assemblies will be subsequently utilized in several studies that will evaluate the reliability of double-sided assemblies, different fluxing techniques, reflow encapsulants for CSPs, and the robustness of through-hole solder joints.

Wafer level CSPs were assembled using different fluxing techniques including flux jetting, flux dispensing, and flux dipping with a Thin Film Applicator (TFA).

Chip capacitors and chip resistors were assembled on the bottom side of double-sided assemblies to study the influence of board stiffness on the thermal cycling fatigue resistance of flip chip CSPs that were assembled on the top side of the test boards.

THCs were assembled using two different solder pastes and squeegees angles (60° and 45°). The effects of these two parameters on the robustness of the resulting solder joints were evaluated through pull tests and hole-fill studies and are included in this report.

The solder pastes used in this assembly were eutectic Sn63/Pb37 (Type IV, no-clean) and Sn96.5/Ag3/Cu0.5 (Type III, no-clean). Boards with an alpha immersion silver surface finish were used for all the assemblies.

X-ray imaging, electrical continuity tests, cross-sectional analysis, C-mode scanning acoustic microscopy, and pull tests were used to characterize the assemblies of surface mount and through-hole components.

Several time-zero failures were observed during the reflow encapsulant and flux-only assembly studies. One instance of a component-level defect was also recorded. Surface finish degradation was observed on a site that was designed for the assembly of chip resistors. This resulted in incomplete solder wetting and open solder joints. For the THC assemblies, stencil printing using 45° angle squeegees resulted in greater percentage hole-fill compared to 60° angle squeegees, which contributed to higher pull forces of the leads.

Characterization Of Wafer Scale And Elastomeric Based Csps
Authors: David Esler and K. Srihari

Abstract: Integrated flux assembly process parameters similar to those used for lead-free flip chip assembly were evaluated for the assembly of a lead-free, fine pitch, Wafer Level Chip Scale Package (WLCSP). Solder paste and flux-only assembly processes were compared in terms of setup, joint formation, flux residue, and standoff. Sn/Ag/Cu bump and paste metallurgy was used for this experiment. Standard fine pitch Surface Mount Technology (SMT) solder paste printing processes were compared with two fluxing techniques for assembly. Solder paste printing was accomplished using a DEK 265 GSX stencil printer. Application of paste flux was carried out using a Universal GSM Thin Film Applicator (TFA). The Asymtek DJ-2200, a stand-alone automated fluxing unit, was used for liquid flux application.

A flux-only assembly is used in applications where solder paste deposition is either impractical or yields high defect rates such as printing for assembly of fine pitch components such as flip chip. This assembly was performed to evaluate the viability of lead-free flux-only processes in terms of solder joint formation on different board surface finishes. A total of 120 packages were assembled on three board surface finishes including Electroless Nickel – Immersion Gold (ENIG), Immersion Silver (ImmAg), and Copper with Organic Solderability Protectant (CuOSP). The resulting solder joints were studied using cross-sectional microscopy and X-ray analysis to investigate solder bump collapse and wetting of the solder to the pads on the test boards. The WLCSP assemblies were tested for electrical continuity to determine the electrical connection between the WLCSP and the Printed Circuit Board (PCB). The WLCSP assemblies were also subjected to Air-to-Air Thermal Cycling (AATC) reliability testing followed by failure analysis of samples from each assembly type.

Lead-Free And Sn/Pb Leadless Chip Scale Package Reliability
Author: Michael Meilunas

Abstract: The introduction of leadless chip scale packages has been driven by two major factors: the desire for smaller, more space efficient designs and the required elimination of lead (Pb) from electronic products. By removing second level interconnections such as solder balls or component leads, package suppliers are offering leadless Pb-free components with minimal thickness. This approach leaves the choice of attachment material to the assembler.

Between 2000 and 2002 the UIC consortium evaluated 7 leadless designs for a variety of printed circuit board (PCB) pad dimensions, PCB surface finishes and attachment materials (solder pastes and conductive adhesive). Nearly 1000 components were assembled specifically for air to air reliability testing and failure analysis. Both 0/100oC and –40/125oC air to air thermal cycles were used in the reliability study. In-situ monitoring determined when failures occurred, while cross-sectioning and dye penetration analysis were performed to determine failure mechanisms and locations. Three attachment materials were used for these experiments: 96.5/3.5% Sn/Ag paste, 95.5/3.8/0.7% Sn/Ag/Cu paste, and eutectic Sn/Pb baseline solder. Assembly and reliability information concerning the use of a conductive adhesive may be found in a separate report, “Reliability Assessment of Leadless Chip Scale Packages in Air to Air Thermal Cycling”, [1].

“Pb-Free Bga Assembly And Testing Performed At Motorola – Austin, Texas”
Author: Michael Meilunas

Abstract: The 2001-2002 Area Array Consortium developed a round robin experiment to focus on the assembly, reliability and failure analysis of Pb-free ball grid array devices. IBM, Nokia Mobile Phones, Motorola, Rockwell Automation and Universal Instruments combined resources to assemble, test and analyze over 800 devices assembled to copper OSP, electroless nickel / immersion gold, and immersion silver printed circuit boards. Each group was responsible for developing reflow profiles and air to air thermal cycle test conditions. The following paper discusses the procedures and results from Motorola, Austin – who assembled and tested both Pb-free and Sn/Pb BGAs on electroless nickel / immersion gold and copper OSP printed circuit boards. Companion papers have been or will be published as necessary.

Effect Of Silver Content On The Shear Strength Of Bga Solder Joints
Authors: Shafi Saiyed and K. Srihari

Abstract: Recent studies have shown a decrease in the thermal cycling reliability performance of solder bumped area array devices that are assembled utilizing Sn/Ag/Cu alloys onto immersion silver finished Printed Circuit Boards (PCBs) [Anselm, 2002]. This experiment attempts to correlate the volumetric and compositional content of silver in a solder joint to its mechanical strength to determine if a reduction in the solder joint interfacial strength is found with increase in silver content. Solder joints with varying silver contents were prepared and tested utilizing a ball shear test. As-assembled (time zero) solder joints as well as solder joints that were subjected to various levels of thermal aging at 150°C were evaluated. Fracture surface analysis using Scanning Electron Microscopy (SEM) and elemental analysis using Energy Dispersion X-ray (EDX) were also performed to correlate the surface morphologies to the experimental conditions.

The results indicated a ductile failure mode across all the experimental conditions. The fracture was observed in the bulk solder. Analysis of the shear force data failed to indicate any significant trends with respect to the amount of silver in the solder joints. At time zero, solder joints with a higher volume content of silver showed higher shear strength values. However, on thermal aging, these joints showed a larger degradation in shear forces. Conversely, solder joints with a low volume content of silver showed comparatively low shear strength values at time zero. However, they indicated a lower degradation in shear forces on thermal aging. No such trends were observed in solder joints with the volume content of silver lying between the ‘high’ and ‘low’ conditions. In addition, no clear inferences could be drawn from the results, based on the percentage composition of silver in the solder joints. The fracture surface analysis of representative samples indicated different morphologies for non-aged and thermally aged samples, thus indicating a change in the interfacialintermetallic structure.

However, no direct link between silver content, interfacial strength, and intermetallic structure formation could be made from the results found in this current study.

Effect Of Printed Circuit Board Surface Finish On The Air To Air Thermal Cycle Reliability Of Chip Scale Packages Part 1
Author: Michael Meilunas

Abstract: This report intends to describe the assembly and test of several Pb-bearing chip scale package (CSP) designs on electroless nickel / immersion gold (ENIG), immersion silver, and copper OSP printed circuit boards (PCB). The main focus of the research is to determine if the air to air thermal cycle reliability of the CSPs is significantly affected by PCB surface finish. Package types included flexible CSPs, micro leadframe CSPs, wafer level CSPs, laminate based CSPs, and a ceramic CSP.

Effect Of Silver Content On The Shear Strength Of Bga Solder Joints
Authors: Shafi Saiyed, Vinod Mohan and K. Srihari

Abstract: In this research, the effects of reflow profile and reflow atmosphere on the wetting ability of Copper Organic Solderability Preservative (Cu OSP), Electroless Nickel/Immersion Gold (ENIG), immersion tin, and immersion silver surface finishes were evaluated. This report contains the results of a set of experiments that were conducted to determine the relative comparison of the wetting ability of Sn/3.8Ag/0.7Cu and eutectic Sn/Pb solder alloys on test coupons having alternative surface finishes. The test coupons were reflowed using ramp-soak-ramp and direct ramp profiles in ambient air and nitrogen atmospheres.

Wetting ability was determined using an area of spread test. For Sn/Ag/Cu alloy, reflow in air resulted in lower wetting ability than reflow in nitrogen atmosphere on Cu OSP, immersion Sn, and immersion Ag surface finishes. However, for ENIG surface finish, comparable diameters of spread were obtained for reflow in air and reflow in nitrogen. The wetting ability of eutectic Sn/Pb alloy was unaffected by a change in profile or reflow atmosphere. However, with the Sn/Ag/Cu alloy, improved wetting was obtained with a direct ramp profile as compared to a ramp-soak-ramp profile.

A mechanical robustness test was performed by reflowing pre-formed solder spheres onto each surface finish and subjecting the assembled solder joints to a ball shear test. Ductile time-zero failures were observed in Sn/Pb and Sn/Ag/Cu solder joints on Printed Circuit Board (PCB) pads having Cu OSP, immersion Sn, and immersion Ag surface finishes. Such ductile failures resulted from ramp-soak-ramp and direct ramp profiles in air and nitrogen atmospheres. The energy-to-break for Sn/Ag/Cu solder joint was higher than Sn/Pb solder joints for all the reflow conditions that were considered. Of the 116 solder joints that were tested, four time-zero brittle failures were observed in Sn/Ag/Cu solder joints on attachment pads with ENIG finish.

Qfp Assembly And Lead Pull Study (Alternate Surface Finishes)
Authors: Muffadal Mukadam and K. Srihari

Abstract: This report summarizes Quad Flat Package (QFP) assembly details along with the lead pull test results carried out on three different QFP component lead finishes. The lead finishes under consideration were tin (Sn), tin-copper (SnCu), and tin-lead (SnPb). In this experiment, two different steam age preconditioning levels (i.e. 1 hour and 8 hour) were used along with a baseline zero hour steam age (or no steam age). Moreover, three different post assembly (before lead pull test) temperature aging conditions (i.e. 0 hour, 500 hour, and 1000 hour) have been planned for the project. This report summarizes lead pull results at time zero (with no temperature aging).

The assembly was conducted on UIC demo boards. Three 208-leaded QFP components were assembled on each of the test boards. Two different solder pastes were used for the assemblies, tin-silver-copper (96.5Sn/3.0Ag/0.5Cu) and tin-lead (Sn/37Pb). Lead pull tests were performed on an Instron materials testing machine.

The assemblies were characterized by visual inspection, X-ray inspection, and cross-sectional analysis. Moreover, microscopic examination of the fractured pads after lead pull tests was performed. The degree of voiding, number of non-wetting cases, and number of pad rip off cases was summarized for all the components tested.

The purpose of the study was to evaluate the three different component lead finishes using steam age preconditioning and temperature aging. This evaluation is performed on the basis of solder joint strength measured by lead pull test. The effects of steam age preconditioning on solder voiding, wetting, fillet formation, and solder joint strength has been studied. Moreover, the degradation in solder joint strength with temperature aging for the different lead finishes is investigated.

Pull Test Evaluation Of Through-Hole Components Assembly
Authors: Hendra Hartono, Shiva Kalyan Mandepudi and K. Srihari

Abstract: Pb-free solder alloys being used in wave soldering and Alternative Assembly and Reflow Technology (AART) processes were evaluated for the robustness of through-hole solder joints formed. An experiment was performed to evaluate the strength of these Pb-free solder joints, with eutectic Sn/Pb assemblies used as a baseline for comparison.

Five types of headers were assembled on multi-layered, FR-4 Printed Circuit Boards (PCBs), with assembly parameters such as the Plated Through-Hole (PTH) diameter, pad size, and stencil aperture area being varied. The assemblies were built using eutectic Sn63/Pb37, Sn95.8/Ag3.5/Cu0.7, and Sn96.5/Ag3.5 solder alloys as described in [Hartono, 2001] and [Hartono, 2002]. The pull test was used to assess the strength of the through-hole solder joints.

The pull force of the AART assemblies using eutectic Sn/Pb and Sn95.8/Ag3.5/Cu0.7 alloys was comparable. However, Sn96.5/Ag3.5 wave soldered assemblies had higher pull force when compared to the Sn95.8/Ag3.5/Cu0.7 AART assemblies.

Effect Of Deposit Size On The Quality Of Lead-Free Solder Joints: An Analysis Using Thermogravimetry
Authors: Vinod Mohan, Denis Barbini and K. Srihari

Abstract: Previous studies using lead-free solder have shown a direct correlation between solder paste deposit size and the quality of the resulting solder joints when reflow is performed in ambient air. In these studies, the smaller sized paste deposits (with a diameter less than 35 mils or 0.889 mm) failed to completely reflow and form acceptable joints. However, the probability of forming a successful solder joint increases greatly when the deposit size had a print diameter greater than 35 mils or 0.889 mm. This effect was evident when reflow was performed using a traditional ramp-soak-spike or a direct-ramp reflow profile. This effect, was the most pronounced while utilizing a ramp-soak-spike profile in open air. Assembly experiments have shown that for small (chip size package, < 0.8 mm pitch), lead-free solder paste deposits, the solder did not completely reflow, while larger (Ball Grid Array >1.0 mm pitch) lead-free printed solder paste deposits had completely reflowed and formed acceptable joints when utilizing a direct-ramp profile. It was hypothesized that, in the case of smaller joints, the percentage of flux that evaporated during the soak stage of the thermal profile was higher as compared to the larger joints, resulting in insufficient flux availability during the reflow stage. This may prevent complete removal of oxides from the metal surfaces when reflow is performed in air.

In this research study, Thermogravimetric Analysis (or TGA) was utilized to determine the effect of deposit volume on the flux evaporation rates. Lead-free Sn/3.8Ag/0.7Cu solder paste was reflowed using a ramp-soak-spike and a direct-ramp profile, and the characteristic weight loss was determined for different deposit volumes. It was observed that the percentage weight loss prior to the reflow stage was greater for a smaller deposit size (20 mils or 0.508 mm in diameter) as compared to larger deposit size (60 mils or 1.524 mm and 100 mils or 2.54 mm in diameter).

Uic Pb-Free Bga Testing: An Update To Thermal Cycling Reliability Analysis Of Lead-Free Solder Alloys
Author: Michael Meilunas

Abstract: The Area Array Consortium completed an extensive lead-free ball grid array (BGA) evaluation culminating in an award winning paper published by the IPC. The program, whose goal was to determine the thermal reliability of selected lead-free solder alloys in electronics packaging, began in 2001 and ran through the 2002 consortium. The information presented in this report is Universal Instruments’ portion of the round robin experiment conducted by IBM, Motorola, Nokia, Rockwell Automation and UIC. This report contains up-to-date information concerning the thermal fatigue resistance of the chosen alloys used to assemble components to FR-4 printed circuit boards (PCB). Additionally, problems and issues associated with the components and alloys are discussed. Information pertaining to the assembly conditions, pre-test characterization, and test procedures are included in this report. Failure analyses and lifetime analyses are discussed, when applicable. This paper is provided to update consortium members on the status of the lead-free program at Universal and the information presented may or may not agree with that of the other round robin participants.

This paper provides a comparison of the air-to-air thermal cyclic reliability and associated failure modes of second level interconnects in lead-free, 1.27 mm pitch, 256 I/O BGA devices with eutectic tin-lead assemblies. Both electroless nickel/immersion gold (ENIG) and copper OSP test board surface finishes were included in this study. The assemblies were subjected to 0/100oC accelerated thermal cycles. Solder joint failures were determined with in-situ event detection and verified by resistance measurements, x-ray, cross-sectioning and dye penetration. Elemental analysis was performed on selected failed solder joints. The results of the experiment indicate that the average solder fatigue life of the lead-free alloys investigated was higher than that of the tin-lead solder. However, the fundamental crack propagation behavior of the lead-free alloys was not the same as the tin-lead samples. Failure analysis revealed that intermetallic formation, fatigue crack characteristics, and solder fatigue propagation mechanisms associated with the lead-free alloys were not common to the tin-lead samples. In addition, lead-free solder joints evaluated in rigorous failure analysis show unique features such as stress voids, crack path redirection around intermetallic formations, vertical cracking and spalling of portions of the solder joint, which are not common in traditional tin-lead BGA solder joints.

Packaged Devices And Lead-Free Activities Summary
Author:Anthony A. Primavera

This report is a final overview and summary of the area array consortium activities related to assembly and test of packaged devices and additionally discusses lead-free soldering activities. This overview is a summary of the consortium development for the year 2002. A separate summary is presented in [Borgesen, 2003 – Optoelectronics Overview] for the year 2002 Opto-electronics program, and in [Blass, 2003 – Direct Chip Attach Program Overview] for the direct chip attach program. A total of almost 50 reports have been prepared for the year 2002 area array efforts which discuss the following topics:

· Circuit Boards
· CSP/BGA Components
· Assembly
· Rework
· CSP and Reworkable Underfill
· Reliability Testing
· Nickel Gold Metallurgy
· Lead-free Materials
· Lead-free Assembly
· Lead-free Reliability

Some of the projects completed this year were continuations of previous studies, such as thermal cycle testing, while other studies were started and completed within the 2002 work scope. Further information about each topic is available in supporting documents and reports, which are referenced in this report. Additional information is available in the year 2001, 2000, 1999 and 1998 Area Array Consortium CD-ROMs. While activities included both tin / lead (Sn/Pb) as well as lead-free solder alloys, this overview will combine aspects of both technologies where important and relevant. For example, a discussion on rework or assembly will contain issues related to BGA and CSP devices for both lead bearing and lead-free solders. Issues related strictly to lead-free such as wave soldering with lead-free alloys, will be discussed as well. Some of the new activities for 2002 included assembly and reliability assessment of flexible polyimide circuit boards, assembly of land grid array CSPs, and evaluation of surface mount components with a variety of lead-free lead finishes. Each subject is presented in separate reports, and is highlighted in this document.

Air To Air Thermal Cycling Reliability Of Generic Flip Chip Csp On Alternate Surface Finishes Summary
Authors: Shafi Saiyed and K. Srihari

Abstract: With the transition to a lead-free assembly process, there is a definite need to determine suitable surface finishes for Printed Circuit Board (PCB) metallizations that can replaceSn/Pb Hot Air Solder Level (HASL). Electroless nickel/immersion palladium (Ni/Pd), immersion Sn, Copper coated with Organic Solderability Preservatives, and the lead-freeHASLs – Sn/Ag, Sn/Ag/Cu, and Sn/Cu are among the potential contenders for use with a lead-free process. The objective of this study was to determine the effect of the aforementioned surface finishes on the assembly and thermal fatigue reliability of a generic Flip Chip Chip Scale Package (FCCSP).

A 64 I/O, 0.8 mm pitch generic FCCSP with lead-free solder bumps (Sn/4.0Ag/0.5Cu and Sn/3.5Ag) was assembled on test vehicles with lead-free surface finishes using lead-free solder paste (Sn/3.8Ag/0.7Cu and Sn/3.5Ag). The assemblies were tested for electrical continuity and thoroughly inspected using x-ray and cross-sectional analyses to check the integrity of the solder joints. The test vehicles were subjected to accelerated Air–to-Air Thermal Cycling (AATC) test between 0 to 100oC. The air-to-air thermal cycling test consists of 20 minute cycles with 5 minute ramps and 5 minute dwell times at the extreme temperatures. As of writing this report, the assemblies have completed 11000 thermal cycles with failures reported in 21 assemblies out of 67 assemblies that are being tested. Based on the failure data available, packages assembled on immersion Sn and HASL (Sn/Ag/Cu andSn/Cu) pad finishes show higher characteristic lives as compared to Ni/Pd and Sn/Ag HASL pad finishes. The mode of failure that was observed was bulk solder fatigue. The cracks in the solder joint had a shattered appearance, which was consistent across all the surface finishes. This report provides an update on the reliability results obtained from air-to-air accelerated thermal cycling tests.

Characterization And Reliability Of Non-Molded Flip-Chip Bgas And Csps
Author: Michael Meilunas

Abstract: A non-molded component is an electronic package whose die has not been coated with a mold compound, also called an overmold. Traditional BGAs and CSPs require molds in order to shield the active surface of the die from the environment and to provide mechanical support to the first level wirebond connections. However, flip-chip in package BGA and CSP designs encapsulate the active surface of the die and have no need for wirebonds. Non-molded flip-chip BGAs and CSPs are slimmer, lighter, and potentially cheaper than their molded counterparts and may be assembled to printed circuit boards using the same processes as traditional molded components. The following paper describes the characterization and assembly of two non-molded components: a BGA and a CSP; and compares the thermal and mechanical reliability of the packages to equivalent molded components.

Drop Test For Underfilled Csp Assemblies
Authors: Murtuza Rampurawala, Mark Dunlap and K. Srihari

Abstract: Chip Scale Packages (CSPs) that are utilized in portable electronic applications are subjected to mechanical stresses that are caused by vibrations, impact loads, bending, shock, and other mechanical stresses. Underfilling CSPs significant improves the mechanical robustness of a CSP assembly and increases its resistance to stresses that are induced by impact, twisting, and vibration loads [Babiarz & Lewis, 2000].

A drop test fixture was designed to simulate free fall of a Printed Circuit Board (PCB) assembly. Drop test was used to evaluate the resistance of underfilled assemblies to mechanical stresses that are exerted on them due to sudden impact loads. The drop test setup was characterized to determine the forces experienced by electronic components at various locations on the PCB. The test board with the component assemblies was setup in the fixture such that the PCB did not directly contact the concrete base, but the impact forces were transferred to the test board through an organic strip. This setup emulates the behavior of an actual PCB assembly within a cell phone housing when it is dropped from a height of several feet. The impact forces are transferred to the PCB through the casing around the cell phone.

Different underfill materials and their associated underfilling techniques were evaluated in this study. Capillary flow underfills, partial underfills, and reflow encapsulants were considered in this research. Three different CSP devices were underfilled using the set of underfills mentioned above and subjected to a drop test. The components were subjected to multiple drops with impact acceleration reaching 700 to 1000 G. Additional mass was added to each component to increase the resulting shear load (force) on each solder joint. Weights attached to the device body to resulted in electrical failure of the assembly within several drops. The underfilled samples showed significant improvement in resistance to impact stresses that were generated during the drop test as compared to the non-underfilled samples. Partially underfilled samples showed an increase in reliability of 4.5X to 5.5X when compared to non-underfilled samples. No failures were recorded in assemblies that were underfilled using reflow encapsulants and capillary flow underfills when tested up to 50 drops.

Examination Of Failures In Electroless Nickel Immersion Gold (Enig) Pbsn Solder Joints
Author: Eric Cotts

Abstract: A metallurgical study was conducted in an effort to identify and understand the mechanism(s) behind failures of PbSn solder joints on ENIG substrate pads. Testing at Universal Instruments had established a correlation between the substrate supplier and the “brittle” failure of such joints in shear testing before or after aging at elevated temperature. The question was posed whether this was related to the so-called “Ni-Au problem”, the formation of a (Ni, Au)Sn4 layer at the pad surface, which seems to have been plaguing the industry for almost a decade. If so, this would have contradicted the recently suggested, relatively simple dependence on Au-thickness.

Sets of samples that did and did not exhibit the brittle failure were selected and provided by Universal Instruments. An in-depth metallurgical investigation showed no correlation with the formation of a (Ni, Au)Sn4 layer at the pad surface for these samples. In fact, little if any (Ni,Au)Sn4 was found at pad interfaces for these samples. Rather, almost all brittle failures were found to be caused by the so-called “black pad” phenomenon, or were at least related to this phenomenon. Some cases involved additional phase formation at the interface between the Ni3Sn4 layer and the Ni(P) during aging. In a few cases failure seemed related to the formation of a (Cu, Ni)6Sn5 layer. The failures should be preventable by proper control of the plating chemistries, including the immersion Au formulation.

Reliability Of Double-Sided Bga And Qfp Assemblies
Author: Shiva Kalyan Mandepudi

Abstract: The increasing demand for smaller and faster products in the electronics industry has spurred the movement from peripherally-leaded Quad Flat Packs (QFPs) to the increased use of Ball Grid Arrays (BGAs). To further meet the requirements of the electronics industry, BGAs are being assembled on Printed Circuit Boards (PCBs) in a back-to-back double-sided fashion to help reduce the required routing space and improve electrical performance. Mirror imaged BGAs are gaining importance in high-speed networking applications. However, a significant concern with these assemblies is their reliability as evaluated through thermal cycling.

In this research, double-sided back-to-back BGA assemblies and mixed assemblies involving BGAs and QFPs were investigated. The reliability of the assemblies was evaluated through air-to-air thermal cycling. Single-sided assemblies were used as a baseline for comparison. In addition, the effect of solder joint standoff on thermal cycling reliability of double-sided and single-sided assemblies is also evaluated.

256 I/O Plastic Ball Grid Arrays (PBGAs) and 208 I/O QFPs were assembled on 62 mil, multilayered FR-4 PCBs using eutectic Sn63/Pb37 (Type III) solder paste. The PBGA single-sided assemblies had two to three times the reliability of double-sided mirror imaged assemblies. BGAs in BGA/QFP (BGA on the top side and QFP on the bottom side) assemblies had significantly higher reliability when compared to mirror imaged BGA assemblies. In fact, the reliability of these assemblies was comparable to the reliability of single-sided BGA assemblies. Irrespective of the type of assembly (mirror imaged BGA, BGA/QFP, single-sided BGA, single-sided QFP), the primary mode of failure observed was bulk solder fatigue. This report summarizes the thermal cycling reliability data for the various double-sided assemblies that were investigated.

Reliability Of Double-Sided Csp Assemblies
Author: Shiva Kalyan Mandepudi

Abstract: High-density board level assemblies, such as double-sided Chip Scale Package (CSP) assemblies, are gaining prominence as the size of electronic products decreases. A critical issue in double-sided CSP assemblies is the reliability of the device-to-board level attachment. This research evaluated the reliability of double-sided CSP assemblies through thermal cycling. Various scenarios, including mirror imaged double-sided CSP assemblies, offset double-sided CSP assemblies, and double-sided assemblies with different components were considered. It is expected that as the flexure in the form of effective board stiffness increases, the amount of thermally induced strain the assembly can accommodate will be reduced. The effective stiffness can increase by various means including increasing the overall PCB thickness, increasing copper density, changing board materials and by assembling components on the back side of the PCB.

Flip Chip Chip Scale Packages (FCCSPs) and ceramic chip capacitors were assembled on 62 mil, multilayered FR-4 Printed Circuit Boards (PCBs) using eutectic Sn63/Pb37 solder paste. Assemblies were subjected to air-to-air thermal cycling to evaluate their reliability and to three point bend testing to determine local stiffness. Testing revealed that the reliability of FCCSP assemblies decreased with an increase in the localized board stiffness. Single-sided FCCSP assemblies had two to three times the reliability of double-sided mirror imaged FCCSP assemblies. In addition, offsetting the bottom side FCCSP by 50% with respect to the top side FCCSP, translated into a 30% increase in thermal cycling reliability when compared to mirror imaged assemblies. The primary mode of failure that was observed was bulk solder fatigue. This report summarizes the reliability data obtained from thermal cycling double-sided CSP assemblies.

“Reliability And Failure Analysis Of 1.0mm Pitch, High I/O Ball Grid Array Packages”
Author: Michael Meilunas

Abstract: This paper discusses the air to air thermal cycle reliability of high I/O count ball grid array (BGA) devices. An overview of the packages, printed circuit boards (PCB), assembly process, and test methods is provided. Reliability estimates were computed using 2-parameter Weibull plots. Failure analysis included cross-sectioning, dye and pry, and SEM evaluations. Variables studied included PCB pad size and PCB thickness.

Reliability And Failure Analysis Of Stacked Die Chip Scale And Land Grid Array Packages
Author: Michael Meilunas

Abstract: This paper discusses the air to air thermal cycle reliability of stacked die chip scale packages (CSPs) and stacked die land grid array (LGA) devices. A brief overview of the packages, printed circuit board (PCB), assembly process and test methods are provided. Reliability estimates were computed using 2-parameter Weibull plots. Failure analysis included cross-sectioning, dye and pry, and SEM evaluations. In addition to CSP versus LGA, variables studied included PCB pad size and package substrate thickness.

Reliability Modeling Of Area Array Packages Using Finite Element Analysis
Author: James Pitarresi

Abstract: This update report summarizes the effort by the Mechanical Engineering group at Binghamton University toward the electronics packaging challenges of the Universal Instruments Area Array Consortium. Specifically, this update covers the period from January 1, 2002 through June 30, 2002 for Finite Element Analysis (FEA) work supervised by Dr. Anthony Primavera. All Finite Element Models (FEM) are available to consortium members and may be acquired by contacting the author or Dr. Primavera.

A finite element based approach for estimating the thermal cycling reliability for chip scale packages is presented. Three-dimensional finite element models were built for each of the packages studied. The methodology is based on Anand’s viscoplastic constitutive law for the solder response stress-strain response. To test the validity of this constitutive relation, the displacement in the solder joint for a generic CSP was predicted to within 20% of that measured using moiré interferometry. Darveaux’s crack growth-rate model for solder fatigue was used as the solder failure metric. A Weibull two-parameter failure distribution was assumed. The characteristic life of each package was estimated for the 0oC to 100oC, 20-minute cycle. Good correlation between the measured and predicted life was observed for many of the packages that have completed their testing. The correlation was typically within the expected 2.0X error band of the method. In addition, some packages were studied using field-use thermal profiles: one cycle per day 10oC to 45oC, one cycle per day 20oC to 60oC, and 16 cycles per day (90-minute) 20oC to 60oC. It was found that the acceleration factors for these cases were greater than fifteen times that of the 0oC to 100oC, 20-minute cycle. It was found that wafer-scale CSPs present new modeling challenges due to their small size and inclusion of thin material layers in the under bump metallurgy. Lead-frame packages also present challenges in that Darveaux’s crack propagation method was not developed for the type of solder joint that they generate. To address these modeling difficulties, substructuring, submodeling, and constraint equations have been used with success. Later reports will present these techniques in more detail. Further work needs to be done to improve the modeling results for these packages.

Using moiré interferometry, the relative displacement in the corner solder joint of a wafer-scale CSP was measured and compared with that predicted by the finite element model. The model predicts a difference of approximately 10%. This is excellent correlation and adds confidence in the solder constitutive model and finite element modeling approach.

Reliability Modeling Of Double-Sided Area Array Packages
Authors: James M. Pitarresi and Satish Parupalli

Abstract: This report summarizes the modeling efforts of the Mechanical Engineering group at Binghamton University toward double-sided area array electronic assemblies.

A critical issue in double-sided assemblies is the thermal cycling reliability performance of the device-to-board level attachment. In this report, the effects of components placed on opposite sides of the test board were studied. The components included CSPs, BGAs, and QFPs. Actual components were assembled to FR4 test boards and their reliability was measured by Universal Instruments Corporation’s Surface Mount Lab using a 0 to 100°C air-to-air accelerated thermal cycle. Cycles-to-failure were documented for all assemblies and then used in correlation studies with finite element model predictions.

Finite element models were constructed with ANSYSâ version 5.6. The models incorporated nonlinear and time-temperature dependent solder material properties to estimate the fatigue life of the solder joints and obtain an estimate of the overall package reliability using Darveaux’s crack propagation method and assuming a Weibull failure distribution. In addition, moiré interferometry was used to study the displacement distribution in the solder joints at specific locations in the packages. The models were able to predict the double-sided assembly reliability within the expected ±2X error band for both mirror-image PBGAs and CSPs and for 50% overlap CSPs. Moiré images confirmed the location(s) of the most highly strained solder joint(s) in the assemblies. Further studies are needed to correlate displacements between measurement and models and perform parametric investigations involving other assembly configurations.

Thermal Cycle Reliability Analysis Of Sn/Pb And Pb-Free Bgas Assembled With Sn/Ag/Cu Solder Paste
Author: Michael Meilunas

Abstract: The 2001-2002 Area Array Consortium developed a round robin experiment to focus on the assembly and reliability of lead-free ball grid array devices. IBM, Nokia Mobile Phones, Motorola, Rockwell (Collins) and Universal Instruments combined resources to assemble, test and analyze over 800 devices assembled to copper OSP, electroless nickel / immersion gold, and immersion silver printed circuit boards. Each group was responsible for developing reflow profiles and air to air thermal cycle test conditions. The following paper discusses the results obtained by Rockwell – who performed a mixed assembly on immersion silver printed circuit boards. Companion papers have been or will be published as necessary.

Assembly And Reliability Of Reworkable Underfills For Csp Applications
Authors: Murtuza Rampurawala, Arun Gowda and K. Srihari

Abstract: Chip Scale Packages (CSPs) have found widespread use in hand held devices and portable electronics. Mechanical stresses induced by vibration and impact related shocks pose serious reliability concerns for CSP assemblies. Underfilling CSP assemblies can significantly increase their mechanical strength and robustness. The ability to rework CSP assemblies is of substantial importance considering the occurrence of assembly defects, field failures, and design changes. Reworkable underfills offer the advantage of reworkabilityover conventional underfills and are ideal for CSP applications.

Reliability studies were performed using accelerated testing methods on four different packages in combination with three underfills. The reliability data for non-underfilledassemblies, underfilled assemblies, and reworked underfilled assemblies are compared. Accelerated testing conditions using air-to-air thermal cycling (0 to 100oC, 20 minute cycle) and mechanical testing (cyclic torsion test) was used to compile reliability data. The samples were tested at 3.0 degrees of deflection in the torsion test.

Results indicate that underfilled samples survive approximately 3 to 10 times longer than non-underfilled samples in torsion testing. The cycles to failure varied depending upon the type of underfill and the package used. Reworking underfilled samples reduced reliability (in comparison to underfilled assemblies) by approximately 30 to 50% in torsion testing. Preliminary thermal cycling results have shown early failures in samples underfilled with the Hysol CNB-18 underfill material. Thermal cycling tests are still in progress (2300 cycles).

Assembly And Rework Of A 2577 I/O Bga
Authors: Arun Gowda, Ken Tojima, Jabil Circuits, David Esler and Michael Meilunas

Abstract: Package BV is a 52.5 mm, 2577 I/O, 1.0 mm pitch flip chip Ball Grid Array (BGA) device that is utilized in high-end information systems and communications applications. The following report focuses on Package BV assembly and rework process development utilizing a 93 mil thick printed circuit board.

A detailed description of Package BV and the printed circuit board is presented in this report. The assembly process (solder paste printing, component placement, reflow soldering) and the rework process (thermal profiling, component removal, site redressing, component replacement) are documented.

X-ray and cross-sectional analysis were used to qualify the results. One original BGA assembly was defective due to solder bridging at the corners of the device. Ten of the assemblies were selected and reworked successfully with a flux-only process. Ten additional assemblies were selected and reworked with a paste printing process.

Characterization Of Air-Vac Drs24ncxx.Hed Rework Station
Authors: David Esler and K. Srihari

Abstract: The Air-Vac DRS24NCXX.HED is a hot gas rework station. This rework station is designed to accommodate the rework of area array devices such as Ball Grid Arrays (BGAs) and Chip Scale Packages (CSPs). In this research, the Air-Vac DRS24NCXX.HED rework station was characterized. The capability of the rework station to perform processes such as component removal, site redressing, and component replacement was characterized.

After the initial setup of the rework station, several representative assemblies were reworked. Rework processes for wafer level CSP and BGA assemblies were developed on the Air-Vac rework station. The component removal, site redressing, and component replacement processes were optimized. Thermal profiles were developed for each rework, component removal, site redressing, and component replacement process. The rework nozzles were characterized in terms of the board temperature, component temperature, and adjacent component temperature during reflow.

The site redressing tool on the rework station was extensively characterized. Optimal settings for the site redressing of tin-lead and lead-free assembly sites were determined. A range of assembly sites was considered for the site redressing study, with the sites varying in pitch, I/Os, and solder volume. The redressed sites were then evaluated based on the amount of solder remaining on the attachment pads after redressing, its consistency, and the shape of the final deposit of solder on the pads. Sample packages were also assembled onto redressed sites to evaluate the wettability of the surface.

This report contains an extensive characterization of the Air-Vac DRS24NCXX.HED rework station. The capability of the rework machine to successfully rework area array devices is discussed.

Rework Of Underfilled Chip Scale Package Assemblies
Authors: Arun Gowda and K. Srihari

Abstract: The underfilling of Chip Scale Package (CSP) assemblies offers a significant increase in the mechanical strength and robustness of the assembly. Underfilling a CSP will improve the second level interconnection’s resistance to stresses induced by impact, torsion, vibration, and thermal fatigue. The reworkability of underfilled CSP assemblies is of substantial importance considering the occurrence of design changes, manufacturing defects, and field failures. Rework of underfilled CSP assemblies poses many challenges in terms of removal of the defective component and redressing of the site to remove the underfill and residual solder.

Rework processes were developed for four different packages in combination with four underfills. Thermal profiles for component removal and replacement were developed for all the underfills. Several automated sequences were attempted to remove components using an independent pick-up tube, but the vacuum force was insufficient to overcome the adhesion of the underfill between the component and the board. A modified removal sequence and manual twisting motion was required to remove the defective component. Site redressing was performed using a rotary tool and dental brush. The brushing was followed by removal of excess solder using the soldering iron and wick method. New components were placed on the redressed site and soldered. The reworked assembly was then underfilled.

A high level of operator involvement was required to rework the underfilled CSPs. The two Loctite 227576_A underfills (ver 1.0 and ver 2.0), which are two versions of the same underfill, could not be satisfactorily removed by mechanical brushing followed by residual solder removal using the soldering iron and wick method. Recommendations from Loctite Electronics for site redressing include site scavenging, which removes the residual solder and part of the underfill material, followed by mechanical brushing at 30000 rpm. Since a site scavenging system was not available during this study, a soldering iron and wick method was used to redress the sites. The use of the manufacturer’s recommendations for site redressing may have resulted in the complete removal of the underfill material from the rework site.

Mechanical brushing followed by residual solder removal using soldering iron and wick method was successful in redressing rework sites assembled with Hysol and Emerson & Cuming underfills. CSP assemblies using both these underfills were successfully reworked.

The reliability of the reworked samples was evaluated through air-to-air thermal cycling and torsion testing. The results of the reliability are experiments are presented in Rampurawala, et al. [2002].

First-Level Assembly And Reliability Of An Overmolded Flip Chip Csp
Author: Antonio Prats

Abstract: This report documents the first-level assembly and reliability testing of an overmolded flip chip CSP. Prior to assembly, the substrate and die were characterized and the variations used to perform computer simulations on assembly yield. The only defects during assembly were found on the pad sites predicted by the software.

Voids were found after underfilling which were due to features on the wafer. Transfer overmolding caused solder extrusions, however most of these disappeared after the parts were sent through reflow in the JEDEC test. Most electrical failure occurred to die with thick fillets and delamination.

Thermal Cycle Reliability Of Flip Chip Assemblies Built On A Stiffened Polyimide Flex Substrate
Author: Daniel Blass

Abstract: Flip chip assemblies were built on a polyimide flex substrate that had the flip chip region stiffened with a strip of either 10 or 20 mil thick stainless steel. The assembly variations included three capillary flow underfills, one no-flow underfill, substrates from two vendors, and substrate pre-bake. The pre-bake was either 2 hours at 125°C or no bakeout with only 2 minutes of preheating at the underfill dispense temperature. The assemblies were tested in air thermal cycling between 0°C and 100°C. Testing was stopped after 4867 cycles.

The best reliability was achieved with Loctite FP4531 and the Loctite 3568 reworkable underfill. At most, 36% of the assemblies failed for a particular combination of chip, substrate, and pre-bake condition and most combination had no failures by the end of cycling. All failures with FP4531 occurred with the thicker stiffener and most were on substrates that were not baked out. Most of the 3568 failures were with the thinner stiffener but there was no preference for pre-bake. Few fillet cracks were observed with FP4531 but were more common with 3568. Loctite 3568 even had some large corner fillet cracks but these had not yet led to corner delamination. With or without pre-baking, no underfill delamination was observed for either FP4531 or 3568.

If the substrates were not baked, Namics U8433L performed as well as the FP4531 and 3568. Without pre-bake, only three of 76 chips failed. With pre-bake, however, 70% of the chips failed. Most of the failures on pre-baked substrates were caused by fillet cracking and corner delamination. An examination of the fillets found that pre-baked substrates had thicker fillets. This unintentional variation shows why careful failure analysis and process control are critical for reliability testing. No delamination of the U8433L was observed except for the corner delamination.

The earliest failures were with an unfilled no-flow underfill, Loctite FF2200. The no-flow performed better with the thicker stiffener with none of the chips having more than 40% failure at the end of testing. Failure percentages on the thinner stiffener were between 70% and 100%. Fillet cracking was common with the FF2200 but no underfill delamination was observed.

For these flex substrates, a 2 minute preheat in the dispenser was sufficient for the Loctite 3568 and Namics U8433L. Without bake out, Loctite FP4531 showed voiding and thermal cycling failures.

Soldering Evaluation Of No-Clean Fluxes For Flip Chip Assembly In Air
Authors: Ji Hyon Mun and K. Srihari

Abstract: No-clean tacky/paste and liquid fluxes were evaluated for soldering flip chip assemblies in air. Flip chips were assembled on two types of pad finish, Ni/Au and Cu-OSP. A variety of reflow process parameters was investigated.

Only one flux, Alpha Metals 9171 liquid flux, soldered well to the Ni/Au pads with all considered reflow conditions. Two no-clean paste fluxes, Indium TAC23 and Kester TSF-6502, soldered well to Ni/Au pads in shorter direct-ramp profiles. In the same profiles, Kester TSF-6502 soldered well to Cu-OSP pads while Indium TAC23 soldered well in all but the shortest, coolest direct-ramp profile.

Flux Jetting Process Development And No-Clean Liquid Flux Evaluation
Author: Antonio Prats

Abstract: The Asymtek DispenseJet was used to build flip chip assemblies with 14 liquid no-clean fluxes. The process was refined to dispense a minimum of flux. Only Alpha Metals 9171 flux leaves a tacky film, solders well, and leaves behind little to no visible residue. Indium FC-NC fluxes often leave residue, but this might be adjusted by varying the reflow profile. The Alpha Metals flux also performs well in air reflow of flip chips, and is comparable to tacky paste fluxes for LF-2 lead-free assembly. In high temperature JEDEC 3 testing, these two liquid fluxes were not as widely compatible as the paste fluxes, but they were compatible with at least one underfill.

Reliability Comparison Of Fifteen Underfills
Authors: Daniel Blass, Nikhil Vichare, Sarang Kayande and K. Srihari

Abstract: Flip chips encapsulated with 15 underfills were tested in liquid thermal shock (LLTS) between -55°C and 125°C and air to air thermal cycling (AATC) between -40°C and 125°C. The underfills generally ranked similarly in the two tests. The failure modes were typically the same in both tests. Most samples showed delamination starting at the solder joints. This delamination is thought to be caused primarily by vertical cracks through the underfill layer that start around the solder joints. Chips underfilled with the larger of two dispense amount were also likely to have fillet cracking and corner delamination. In both tests, some chips failed without any observable delamination.

Underfills with a wide range of mechanical properties performed well. Considering the high incidence of underfill cracking, fracture toughness would be a very important property but this data was not available from most suppliers.

There was one glaring inconsistency to the ranking of the underfills. Sumitomo CRP-4300A was the best underfill in LLTS but poor in AATC. This underfill has a low Tg of 56°C and is described by Sumitomo as a flexible phenol hardener chemistry. As with all polymers, the mechanical properties of CRP-4300A are dependent on time, temperature, and ramp-rates. In the slower ramp rate of AATC, the underfill has time to relax, and therefore will not protect the solder joints in this thermal cycle. In LLTS, the underfill does not have to relax or creep. This causes the underfill to act like a high Tg, high modulus underfill in LLTS. Another low Tg material, Loctite CNB881-21, did not protect the joints in either test. These results do not mean that this AATC is a better test of reliability than LLTS. Instead, some underfills that perform well in this air cycle might perform poorly with more service-like thermal cycling with slower ramp rates. An underfill that resists creeping or relaxing should be preferred. Despite the poor performance of the low Tg underfills, these may be attractive for use with fragile low-k dielectrics.

High Temperature Jedec Level 3 Moisture / Reflow Sensitivity Testing Of Flip Chip Assemblies
Authors: Daniel Blass, Felix Bruno, Sunil Gopakumar and K. Srihari

Abstract: This report documents six experiments that tested the JEDEC Level 3 moisture/reflow sensitivity of various underfill-flux combinations using lead-free reflow profiles. A total of 1465 flip chips were built with various material combinations. The materials included 32 underfills, 10 no-clean tacky/paste fluxes, and two liquid no-clean fluxes. The test vehicles used either Ni/Au or Cu-OSP pad finishes. The flip chips were bumped with either eutectic Sn/Pb or LF-2 SAC solder. Many combinations of flux and underfill could pass a 260°C reflow with this flip chip. Several flux-underfill combinations passed with Sn/Pb solder but failed with the SAC solder. There were also combinations that passed with Ni/Au pad finish but failed on Cu-OSP pads. This was observed for both solder alloys.

Thermal Shock Comparison Of Sn/Pb Flip Chips Assembled In Air And Nitrogen
Authors: Ji Hyon Mun and K. Srihari

Abstract: This report compares the thermal shock reliability of eutectic Sn/Pb bumped flip chip assemblies built in air and in a nitrogen atmosphere. The flip chip assemblies were fluxed with two no-clean tacky/paste fluxes. Assemblies were underfilled with Emerson & Cuming E1172 and Loctite FP4549. The flip chip assemblies were subjected to Liquid-to-Liquid Thermal Shock (LLTS) from -55°C to 125°C.

No evidence suggested that solder joints reflowed in air were less resistant to solder fatigue. Assemblies built in air failed slightly earlier than assemblies built in nitrogen but the early failures were caused by failure mechanisms that are unrelated to solder fatigue. The chips built in air also averaged more delamination than those built in nitrogen. This delamination was primarily caused by cracking in the underfill layer. The reflow ambient may have changed the flux residues and, consequently, the effect of the flux residue on the underfill’s fracture resistance.

Comparison Of Jedec Level 3 / 260″C Results For Sn/Pb And Sn/Ag/Cu Bumped Flip Chips
Authors: Felix Bruno and K. Srihari

Abstract: Eutectic Sn/Pb and lead-free flip chip assemblies were built with two no-clean tacky fluxes, Indium TAC23 and Kester TSF-6502. The assemblies were underfilled with ten underfill encapsulants. The parts were then subjected to JEDEC Level 3 moisture/reflow sensitivity test with a 260°C peak reflow temperature. After the test, the assemblies were examined for underfill delamination and solder extrusions.

Solder alloy was an important factor in passing the JEDEC test. Of the 20 underfill-flux combinations, 13 passed with Sn/Pb bumped chips compared to 6 with the Sn/Ag/Cu bumped chips. With the lead-free solder, 5 underfills passed with the Kester TSF-6502 flux but just one passed with the Indium TAC23. The Sumitomo CRP-4152R5 underfill passed with both fluxes and both solder alloys.

Accelerated Testing Of Flip Chip Underfill Materials For Thermal Fatigue Induced Cracking
Authors: H. G. Retsos and E. J. Kramer

Abstract: Fatigue crack growth in the epoxy underfill is a major failure mode for flip chip assemblies on organic substrates during thermal cycling, particularly after exposure to moisture. Our objective was to develop a protocol for accelerated thermal fatigue testing that allows us to predict the crack growth under milder service conditions and the realistic geometry of the assembly. To accomplish this task, we measured the growth per thermal cycle da/dN of a crack in a model epoxy underfill for different values of the range in strain energy release rateDG between the extremes of the thermal cycle. The experiments used epoxy-Invar composite disk samples with two diametrically opposed non-interacted cracks in each of them. We periodically measured the growth of the crack from each precrack using optical microscopy after the sample had been cycled a certain number of times between the temperatures Tup and Tl where Tup > Tl and both Tup and Tl were less than the glass transition temperature Tg of the epoxy. We used two types of thermal cycles, liquid – liquid and air – air, in our experiments. For the first type we used water baths and for the second we built a set up using hot air and cold nitrogen gas at the appropriate temperatures. Thermal cycles with different extremes of temperature give rise to different crack growth rates even for the same range in strain energy release rate (same DG). The practical implication of this result is that one cannot rely on da/dN data measured under extreme conditions to predict thermal fatigue crack growth under the milder conditions expected in service. On the other hand our results also show that one can measure fatigue crack growth rates (da/dN vs. DG curves) under realistic (mild) thermal cycling conditions simply by increasing the precrack length. We developed a protocol for aging the underfill at elevated temperatures and controlled humidity. Using this protocol we were able to compare the da/dN vs DG curves for aged samples with those for unaged samples. While aging for three weeks at 45 °C and 85% relative humidity produces little change in da/dN at low DG, da/dN is increased by at least a factor 2 at higher DG.

Comparison Of Jedec Level 3 / 260″C Results For Sn/Pb And Sn/Ag/Cu Bumped Flip Chips
Authors: Nikhil Vichare, Peter Borgesen and K. Srihari

Abstract: The resistance of an underfilled flip chip assembly to thermal cycling is usually limited by either the cracking of the edge fillets at the die corners or the delamination of the underfill from the chip passivation around the individual solder joints. These phenomena strongly depend on the fillet thickness, the underfill, the substrate mechanical properties and thickness, the flux choice, and the moisture exposure and aging history of the parts. The present experiments were performed to cast light on the sensitivity to moisture and aging, together and separately, something which proves to not be adequately addressed by current accelerated test protocols.

A total of 1552 model flip chip assemblies with combinations of three underfills (Loctite FP4549, Namics U8437-3, Honeywell JM8802) and two no-clean fluxes (Kester TSF-6522, Indium NC-SMQ 75) were aged for different lengths of time at different temperatures and levels of ambient humidity. The resulting degradation of thermal cycling performance was quantified in terms of corner fillet cracking or, to a lesser extent, delamination around the joints in subsequent Liquid-to-Liquid Thermal Shock (LLTS) testing. Aging conditions considered included 72 and 144 hours of PCT, 85°C/30%R.H. for up to 3 weeks, 85°C/85%R.H. for up to 3 weeks, and storage in a laboratory ambient or dry nitrogen for up to a year.

Our long term aging experiments revealed that aging (time/temperature) and humidity contribute separately (but not independently) to degradation of the underfill. Even dry storage showed a tendency to reduce resistance to both fillet cracking and underfill delamination. The dependence on flux appeared to start out negligible but increased strongly with time and humidity level. In a few cases a moderate level of exposure (up to 3 months at room temperature) tended to reduce fillet cracking, but eventually more moisture was worse. Loctite FP4549 remained insensitive to ambient aging for up to a year, but the Namics U8437-3 did not. Both materials were, however, much more sensitive to humidity at higher temperatures.

Aatc Reliability Comparison Of Flip Chips Bumped With 95.5sn/4.0ag/0.5cu And 63sn/37pb
Authors: Sunil Gopakumar and K. Srihari

Abstract: The performance of Sn/Ag/Cu and Sn/Pb bumped chips was compared in Air to Air Thermal Cycling (AATC). Chips were attached to circuit boards with OSP-coated copper and Ni/Au pads. The composition of this Pb-free alloy, 95.5Sn/4.0Ag/0.5Cu, is slightly different than the LF-2 alloy from K&S Flip Chip, 95.5Sn/3.5Ag/1.0Cu. The assemblies were underfilled with Namics U8437-3 encapsulant. The one-hour thermal cycle had temperature extremes of -40°C and 125°C. The assemblies were tested for 1000 cycles. No electrical failures or underfill delamination were observed for either the Sn/Pb or the Pb-free flip chip assemblies.

Soldering Defects In Lf-2 Bumped Flip Chip Assemblies With Liquid No-Clean Fluxes
Authors: Sunil Gopakumar and K. Srihari

Abstract: Flip chips bumped with Sn/Ag/Cu (SAC) lead free alloys do not solder as well as the eutectic Sn/Pb bumped flip chips. Using no-clean tacky fluxes, the SAC solder sometimes does not completely wet substrate pads defined by a solder mask trench. Also, poor self-centering is observed with Cu-OSP pad finishes. These SAC wetting defects are observed with tacky fluxes designed for Sn/Pb solder and with newer fluxes designed for the SAC solder.

This experiment investigates soldering with two no-clean liquid fluxes and compares the results to dip fluxing with no-clean tacky fluxes. The liquid fluxes were applied with the Asymtek Jet Dispensing process, commonly called “flux jetting”. With one flux, Alpha Metals 9171, no improvement in defect levels was observed Ni/Au pads. On Cu-OSP pads, this flux gave better soldering than the dip fluxes. On both pad finishes, more defects were observed with the second liquid flux, Indium FC-NC-HT-B. Two reflow oven oxygen levels were used with Cu-OSP pads, 25ppm O2 and 400ppm O2, but there was no difference in defect levels between the two settings.

Thermal Shock Performance Of Lf-2 Bumped Flip Chips On Silver And Tin Pad Finishes
Authors: Sunil Gopakumar and K. Srihari

Abstract: This report examines the thermal shock reliability of SAC-bumped flip chips attached to two silver finishes and two tin finishes. The chips were attached with two no-clean paste fluxes and underfilled with two encapsulants. The assemblies did not receive any extra thermal excursions or preconditioning before cycling. For comparison, chips built on Ni/Au and Cu-OSP pads were tested as well.

The chips attached to the tin finishes and underfilled with Sumitomo CRP-4152 failed the fastest. Chips with this underfill performed better with the silver finishes than those to Ni/Au or Cu-OSP pads. The chips underfilled with Emerson & Cuming E1172 performed best in LLTS with only 3 failures by 4000 cycles and no trends with respect to pad finish were observed for this underfill.

Effect Of Multiple Thermal Excursions On Thermal Shock Resistance Of Sac-Bumped Flip Chips Built On Silver And Tin Pad Finishes
Authors: Sunil Gopakumar and K. Srihari

Abstract: This report examines the effect of extra thermal excursions on the thermal shock reliability of SAC-bumped flip chips attached to two silver finishes and two tin finishes. The chips were attached with two no-clean paste fluxes and underfilled with one encapsulant. After the chips were soldered to the substrate, the assemblies were reflowed three more times before underfilling. After underfilling, the assemblies were subjected to liquid thermal shock testing.

More than 40% of the chips attached to the Omikron White Tin finish had failed by 500 cycles. All other combinations had less than 10% failure at 500 cycles and, in some cases, no failures. By 1000 cycles, however, between and 70% and 100% of the chips in each set had failed. As with SAC-bumped chips attached to Ni/Au or Cu-OSP pads, extra reflows caused a substantial decrease in thermal shock performance.

Evolution Of The Microstructure Of Pb Free Solder On Various Metallizations
Author: Eric Cotts

Abstract: The present reports reviews our current knowledge and understanding of the intermetallic formation and resulting microstructure in Sn-Ag, Sn-Cu, and Sn-Ag-Cu based solder joints.

Assembly Of Lf-2 Bumped Chips On Silver And Tin Pad Finishes
Authors: Sunil Gopakumar and K. Srihari

Abstract: Flip chips bumped with Sn/Ag/Cu (SAC) lead free alloys have not soldered as well to Ni/Au and Cu-OSP pad finishes as the eutectic Sn/Pb bumped flip chips. The SAC solder sometimes does not completely wet substrate pads defined by a solder mask trench. Poor self-centering is also observed with Cu-OSP pad finishes. While fewer defects are observed with Ni/Au pads, the reliability of SAC-bumped flip chips attached to this finish is degraded by multiple thermal excursions.

This experiment investigates soldering to alternative pad finishes. Two types of immersion tin finishes and two types of immersion silver finishes were tested. Wetting defects were still observed with these alternative finishes. In several cases, defect levels were as good as or better than Ni/Au pads, particularly when a lead-free flux was used.

On The Microstructure Of Pb Free Flip Chip Solder Joints
Author: Eric Cotts

Abstract: Much more than was the case for SnPb, the microstructure of no-Pb solder joints is strongly affected by the choice of contact pad metallurgies and, in the case of the popular Sn-Ag-Cu system, the concentration of silver. The present report addresses a particularly silver rich alloy, the Sn95.5Ag4.0Cu0.5 one, comparing flip chip solder joints of this and eutectic Sn/Pb after reflow and various levels of aging for two different substrate pad metallurgies.

Soldering Defects In Lf-2 Bumped Flip Chips Assembled With New No-Clean Sac Fluxes
Authors: Raghu Chaware, Sunil Gopakumar and K. Srihari

Abstract: This experiment evaluated four new no-clean paste fluxes developed for Sn/Ag/Cu solders. The experiment focused on soldering of SAC-bumped flip chips to Ni/Au and OSP-coated copper pads. The first question was whether solder joints formed during reflow. If solder joints did form, the assemblies were carefully examined with an X-ray imaging system to see whether every joint completely wetted its substrate pad.

Two SAC fluxes did not solder well, Heraeus TF69 and Kester TSF-6590. For the other two SAC fluxes, Indium TAC23 and Kester R903, all solder joints did form. Examination for wetting imperfections showed these fluxes were comparable to a eutectic Sn/Pb flux, Kester TSF-6502, when soldering to Ni/Au pads. For Cu-OSP pads, these two SAC fluxes had fewer wetting defects than Kester TSF-6502. Based on previous work with SAC-bumped chips, more assembly is needed to show that these fluxes are consistently better than eutectic Sn/Pb fluxes for Cu-OSP pads.

Jedec Level 3 Testing Of Lf-2 Bumped Flip Chips Assembled With New No-Clean Sac Fluxes
Authors: Sunil Gopakumar, Raghu Chaware and K. Srihari

Abstract: Lead-free flip chips were subjected to the JEDEC Level 3 test with a lead-free reflow profile. The LF-2 bumped flip chips were assembled with three new no-clean paste fluxes developed for the Sn/Ag/Cu (SAC) solder alloy, Heraeus TF69, Indium TAC23, and Kester R903. The flip chips were underfilled with Loctite FP4549 or Namics U8437-3. Chips were attached to both ENIG Ni/Au and Entek Plus OSP-coated copper pads.

Loctite FP4549 with the Kester R903 flux was the only underfill-flux combination passed the JEDEC Level 3 test without delaminating. Chips that failed the test delaminated at the chip passivation-underfill interface. The delamination started near the perimeter row of solder joints. Namics U8437-3 tended to more and larger areas of delamination than the Loctite FP4549.

Overview Of 2002 Flip Chip Research
Author: Daniel Blass

Abstract: The past year’s research has covered a variety of topics in Sn/Pb and lead-free assembly, underfilling, and reliability.

The assembly work focused on lead-free assembly, assembly of eutectic Sn/Pb with air reflow, flux jetting of no-clean liquid fluxes, and evaluation of new reflow encapsulants. Lead-free assembly looked to eliminate wetting defects with new no-clean tacky fluxes for Sn/Ag/Cu solder, flux jetting no-clean liquid fluxes, and switching to immersion tin and immersion silver pad finishes. While none of these was completely successful, it was found that changing the substrate pad design could improve wetting, at least with Ni/Au pads. A narrow process window was developed for air reflow of flip chips bumped with eutectic Sn/Pb. The flux jetting process was refined, but only one no-clean liquid flux gave a robust assembly process. There is also an assembly yield case study on first-level assembly of a flip chip CSP. After characterizing the substrate and chip bumping, our defect prediction software was used to determine which pad designs would give assembly problems. The actual assembly compared nicely to the predictions.

Transfer molding was used in two projects. One examined simultaneous underfilling and overmolding. With a vacuum-assisted process, complete underfilling was achieved of a 5mm perimeter bumped chip. Several mold compounds were used in combination with various no-clean paste fluxes in tests of popcorn resistance and thermal shock reliability. In another project, flip chips were underfilled by capillary flow and then transfer overmolded.

JEDEC Level moisture/reflow sensitivity testing was a large project. Combinations of 32 capillary flow underfills, 4 molded underfills, 10 no-clean tacky/paste fluxes, and two liquid no-clean fluxes were tested to JEDEC Level 3 with a 260°C peak reflow temperature. Many underfill-flux combinations could pass the test without delaminating. The pad finish and solder alloy were important variables. Many combinations that passed with eutectic Sn/Pb bumps would delaminate if the chip had Sn/Ag/Cu solder bumps.

Reliability investigations covered a wide range of topics. Thermal cycling conditions included liquid thermal shock between -55°C and 125°C, air shock between -65°C and 150°C, and air cycling between -40°C and 125°C and between 0°C and 100°C. Flip chip assemblies built on stiffened flex substrate were tested. Reliability of Sn/Ag/Cu bumped flip chips is primarily focused on the metallurgy (pad finish, alloy composition) and the thermal history (aging, thermal excursions, cooling rate during solidification). These factors affect the flip chip solder joint microstructure and thermal cycle reliability.

The effects of long term aging and moisture exposure on the underfill continues to be an important topic. Flip chips were tested in liquid shock after aging for up to a year in eight different temperature/moisture conditions to compare long term results with short accelerated preconditioning. While the effects of time, temperature, and moisture vary with the underfill, the results point to the possibility of using 3 weeks of 85°C/85%R.H. as an equivalent to 1 year of ambient exposure.

Our years of work have been distilled into process guides and software codes. The biggest update has been made to the assembly yield module. The software has been changed from a probability calculation to a Monte Carlo simulation. The program also can now predict electrical opens for rectangular substrate pads.

Assembly Evaluation Of Ablestik Rp-721-3 Reflow Encapsulant
Authors: Ji Hyon Mun and K. Srihari

Abstract: Ablestik RP-721-3 is an experimental reflow encapsulant designed for flip chip assembly. Unlike most reflow encapsulants, this material is not an anhydride curing epoxy. Instead, RP-721-3 is a blend of epoxy and cyanate ester resins.

Soldering defects were observed in three cool SMT reflow profiles. The defects appear to be caused by premature gelling of the underfill. This may be caused by the substrate pads or solder bump acting as a catalyst for this chemistry.

With default placement settings, the chips would shift off the pads. These defects were prevented by increasing the placement force or the hold time. Throughput with the increased settings would still be as fast as with dip fluxing in the placement machine.

Assembly Evaluation Of Indium 319-20-12 Reflow Encapsulant

Authors: Ji Hyon Mun and K. Srihari

Abstract: Indium 319-20-12 is an experimental reflow encapsulant designed for flip chip assembly. There were no placement related defects such as die shifting or floating. It also exhibited good soldering with the tested reflow profiles. Underfill voids were observed in a number of chips. In some cases, voiding appeared to be related to insufficient substrate bakeout. With extra bakeout, voiding was observed only with the shorter direct ramp profiles. These voids were probably caused by placement bubbles that were not able to dissolve prior to reflow.

Assembly Evaluation Of Loctite 3594 Reflow Encapsulant
Authors: Ji Hyon Mun and K. Srihari

Abstract: Loctite 3594 is a reflow encapsulant designed for flip chip assembly. It exhibited good soldering with reflow profiles that have low soak temperatures. Reflow profiles with higher soak temperatures or longer soaks gave soldering defects because the encapsulant gelled before solder joints could form. This limitation makes 3594 less attractive for integrating flip chip with SMT assembly. No placement related defects, die floating or shifting, were observed with the default placement force and hold time. No underfill voids were observed in acoustic microscope images but an underfill void was observed in the trench opening next to a solder joint in a cross-section.

Assembly Evaluation Of Loctite Hysol Ff2200 Reflow Encapsulant
Authors: Ji Hyon Mun and K. Srihari

Abstract: Loctite Hysol FF2200 is a reflow encapsulant designed for flip chip assembly. It exhibited good soldering with the tested reflow profiles. Underfill voids were often observed near the solder joints. These voids sometimes deformed the solder joint shape and also provided a path for solder extrusion.

Reflow Encapsulant Codification: 2002
Author: Antonio Prats

Abstract: This is designed as a companion to the Underfill Process Codification. The aim is to present a guide to reflow encapsulant evaluation and process development. The focus here will be to highlight the differences, and to provide some simple and relatively quick characterizations that are necessary for reflow encapsulants. However, this should not be taken to mean that the establishment of a detailed and broad knowledge base is not important. The establishment of a sizeable knowledge base is strongly recommended, through work done by your materials and equipment suppliers, as well as by yourself during final qualification or the development of processes for individual applications.

This document will also provide guidance for more detailed tests that will help with process development.

Assembly Evaluation Of Sumitomo Crp-4700f Reflow Encapsulant
Authors: Ji Hyon Mun and K. Srihari

Abstract: Sumitomo CRP-4700F is a reflow encapsulant designed for eutectic Sn/Pb flip chip assembly. Even in cool, short reflow profiles Sumitomo CRP-4700F gelled before all the solder joints could form. The required placement force and hold time also slow down the placement process too much. Many underfill voids were observed in the acoustic microscope images.

Characterization Of Substrates And Solder Bump Heights And First-Level Assembly Simulation For Overmolded Flip Chip Csp
Authors: Felix Bruno, Ji Hyon Mun, Satyanarayan Iyer and K. Srihari

Abstract: Substrates from three suppliers, X, Y, and Z, were characterized. The substrate design included four circuits, A, B, C, and D. The pad diameter, mask opening diameter, and themisregistration were characterized for the substrates from the three suppliers. The solder bump heights for flip chips on four wafers, before and after dicing, were measured. The substrate feature dimensions and solder bump height distribution were characterized to study the effect of variation on the placement and the assembly yields.

There was an increased height in the solder bumps after the wafers were diced compared to before dicing. An increase in the solder bump height can be attributed to the location of the wafer from which the diced chips were picked. The results of the yield prediction models indicated no placement defects on either circular or rectangular pad designed substrates for all four suppliers. However, there was a clear effect of solder bump height variation on the assembly yield.

“Assembly Evaluation Of A Filled Reflow Encapsulant, Sumitomo Crp-4750c”

Authors: Ji Hyon Mun and K. Srihari

Abstract: Sumitomo CRP-4750F is a filled reflow encapsulant designed for flip chip assembly. It provided good fluxing and soldering with a variety of reflow profiles including the manufacturer’s recommended reflow profile. The filler particles, however, caused soldering defects. Filler particles trapped between the solder bumps and the substrate pads sometimes prevented joints from forming. Underfill voids were observed in the acoustic microscope images of most assemblies. Increasing bakeout did not reduce voiding.

Jedec Level 3 Testing At 260″C And Llts Cycling Of Transfer Molded Flip Chips
Authors: Raghunandan Chaware and K. Srihari

Abstract: Flip chips built with four no-clean paste fluxes were transfer molded with two chemically similar molding compounds. The process simultaneously underfills and overmolds the chip. All components had one or more molding defects and some were not tested.

A total of 38 components were subjected to a JEDEC Level 3 moisture sensitivity test with a 260°C peak reflow temperature. No chips delaminated from the chip passivation. Thirteen components delaminated from the solder mask under the chip with two popcorning or completely delaminating from the solder mask. The fewest failures were observed with the Heraeus TF38 flux, just one out of eleven chips. The most failures occurred with the Indium FC-NC-LT-C flux.

A subset was then tested with Liquid to Liquid Thermal Shock for 5000 cycles. No delamination was observed. Even chips with some delamination after the JEDEC test did not delaminate further. Electrical failures occurred by 500 cycles with the Loctite 2778-35A compound. First failures with the Loctite 2786-6A occurred between 2000 and 3000 cycles. Fatigue cracks were observed in the solder near the chip UBM.

Jedec Level 3 Testing Of Transfer Molded Flip Chips With 250″C And 260″C Peak Reflow Temperatures
Authors: Felix Bruno and K. Srihari

Abstract: Flip chip components were successfully molded with a vacuum-assisted transfer molding process that simultaneously underfilled and overmolded the chips. The components were then subjected to the JEDEC Level 3 test with peak reflow temperatures of 250°C and 260°C. Only chips assembled onto trench defined pads passed the JEDEC test. Whether the trench designs passed at 260°C depended on the mold compound and flux choice. It is not clear why the Loctite mold compound performed better with the trench design than with a single solder mask window because delamination always occurred at the chip passivation. The Matsushita compound delaminated from the BT laminate when the window mask opening was used, so poor adhesion to the laminate is suspected.

Effect Of Baking At 85″C In Nitrogen On Resistance To Underfill Delamination And Cracking
Authors: Raghunandan Chaware, Nikhil Vichare and K. Srihari

Abstract: The present experiment is a part of an ongoing effort to distinguish and quantify effects of time, temperature, and moisture on the degradation of flip chip underfill. The rates of corner fillet cracking and delamination from the chip passivation around individual solder joints in subsequent cycling were used as gauges of degradation. Model flip chip assemblies were built using the Kester TSF-6522 tacky flux and three different underfills: Emerson & Cuming E1172, Loctite FP4549, and Namics U8437-3. After cure these were baked in a nitrogen oven at 85oC for up to three weeks and then characterized in terms of fillet cracking and delamination.

Underfill Process Codification – 2002
Authors: Antonio Prats, Peter Borgesen, Sandeep Tonapi, Pericles Kondos, Daniel Blass and K. Srihari

Abstract: The capillary flow-driven flip chip underfill process may be taken to include the selection of equipment (dispenser) and material. Creation of the process certainly involves specification of parameters such as bakeout requirements, substrate temperature, needle size, dispense paths (height above the substrate, distance to chip edge, length of pass), dispense rate, needle temperature, volume in each pass, timing of passes, cure parameters. Optimization of the process and specification of the process windows should minimize important variations and account for the inevitable variations (statistics and tolerances).

The present document offers an attempt at a step-by-step approach to the development of such processes: Preparatory work, rapid development of a process for a given application, and troubleshooting. The establishment of a sizeable knowledge base is strongly recommended, through work done by your materials and equipment suppliers, as well as by yourself during final qualification or the development of processes for individual applications.

The individual sections of this document are carefully organized to minimize the amount of experimental work actually required to reach your goals.

Effects Of Temperature On Underfill Degradation
Authors: Raghunandan Chaware, Nikhil Vichare, Peter Borgesen and K. Srihari

Abstract: The present experiment is a part of an ongoing effort to distinguish and quantify effects of time, temperature and moisture on the degradation of flip chip underfill. The rates of corner fillet cracking and delamination from the chip passivation around individual solder joints in subsequent cycling were used as gauges of degradation. Model flip chip assemblies were built using the Kester TSF-6522 tacky flux and three different underfills: Emerson & Cuming E1172, Loctite FP4549, and Namics U8437-3. After cure, these were baked in a vacuum oven at 85oC for up to three weeks and then characterized in terms of fillet cracking and delamination.

Volatilization Of The Ableluxtm Ogrfi146t Optical Adhesive Before And During Cure
Authors: Angela Quintanilla, Peter Borgesen and K. Srihari

Abstract: Experiments were conducted to evaluate the outgassing of the optical adhesive OGRFI146T before, during and after cure. Different amounts of this adhesive were deposited in aluminum pans, always covering the bottom so that the open surface area remained the same. The samples were then irradiated with light and/or thermally post-cured and their weight was measured on a microbalance before and after each cure step.

Volatilization Of The Ableluxtm A4083t Optical Adhesive Before And During Cure
Authors: Angela Quintanilla and K. Srihari

Abstract: Current studies of optical adhesives include experimentation on outgassing before and during cure of the AbleluxTM A4083T. Different amounts of adhesive were deposited in aluminum pans and their weights were monitored at room temperature. Experiments were also conducted to determine the mass loss during irradiation and thermal post cure. Possible redeposition on nearby surfaces was assessed by thermally curing the samples in partially covered pans and monitoring their mass loss.

“On The Loss Of Mass From The Cnb753-42 Optical Adhesive Before, During And After Cure”
Authors: Angela Quintanilla and K. Srihari

Abstract: The volatilization of the UV curable CNB753-42 optical adhesive from Loctite was studied by depositing different amounts in aluminum pans and monitoring their mass before, during and after exposure to UV light for different periods of time at different source-sample distances. Continued mass loss after UV irradiation seemed to indicate that cure might still be incomplete.

Mass Loss From The Cnb897-02 Optical Adhesive Before And During Cure
Authors: Angela Quintanilla and K. Srihari

Abstract: The volatilization of the UV curable CN897-02 optical adhesive from Loctite was studied by depositing different amounts in aluminum pans and monitoring their mass before and during exposure to UV light for different periods of time at different source-sample distances.

Cure And Performance Of Ableluxtm Ogrfi146t In A ‘Realistic’ Configuration
Authors: Peter Borgesen, Sarang Kayande and K. Srihari

Abstract: The present report addresses the cure of the AbleluxTM OGRFI146T optical adhesive in a narrow gap between two solid surfaces, and the resulting properties of the cured material. As observed before for other materials the cure kinetics seem to differ from those measured by DSC of thicker, unconstrained layers and the mechanical properties depend on the combination of cure parameters and layer thickness. The sensitivity to thickness seemed somehow related to thickness dependent effects of exposure to blue light.

Effects Of Gap Size On The Cure And Performance Of The Ableluxtm A4083t Optical Adhesive
Authors: Peter Borgesen, Sarang Kayande and K. Srihari

Abstract: Optoelectronics packaging often involves the deposition and cure of a photocurable adhesive in a narrow gap between two solid surfaces. Not surprisingly, both the cure kinetics and the properties of the fully cured material may deviate substantially from those of the bulk. The AbleluxTM A4083T optical adhesive was cured in two different, realistic, gap sizes in a generic configuration and adhesion used as a qualitative measure of the completeness of cure. The cure kinetics was found to depend on gap size and differ from those measured by DSC of thicker, unconstrained samples. The adhesion of the completely cured material to aluminum varied strongly with thickness (gap size).

Digital Dispensing Of A Filled Material
Authors: Satyanarayan Iyer, Pericles A. Kondos and K. Srihari

Abstract: A large number of individual small deposits of a silver-filled epoxy was dispensed in several sets of experiments, using a Creative Automation Champion 3700 dispenser. The diameter and height of each deposit, and the corresponding scatter, were determined with a WYKO NT 2000 measuring system. The volume of individual deposit could not be calculated because of their shape, but an approximate average volume was estimated by measuring the total weight of the adhesive that was deposited. The smallest average volume was about 17 nl. The effects of dispense parameters such as dot size, dot pause and dispense height on diameter, height and average volume were studied. Diameter, height and volume were seen to have an upward trend with increasing dot size. With increasing dot pause, diameter showed an upward trend but the height had a downward trend. As a result, a weak upward trend was seen for the volume. With increasing dispense height there was a downward trend in diameter and an upward trend in height which cancelled each other so that the average volume remained approximately constant. The scatter in diameter and height changed considerably with dot size, dot pause and dispense height, but the changes did not seem to exhibit any definite simple trend.

Digital Dispensing Of Unfilled Materials
Authors: Satyanarayan Iyer, Pericles A. Kondos and K. Srihari

Abstract: A large number of individual small deposits was dispensed in several sets of experiments, using a Creative Automation Champion 3700 dispenser. The diameter, height, and volume of each deposit were determined with a WYKO NT 2000 measuring system, and the scatter of each set of deposits was calculated. Two liquid adhesives were used for the tests, the Kester SE-CUREÒ 9101 reflow encapsulant and the Ablestik AbleluxTM AA50T optical adhesive. The effects of dispense parameters on the size of the deposits were studied using the AA50T adhesive. For various values of dot size and dot pause considered, the average volume of the AA50T dots remained almost the same. Also, the scatter did not have a definite trend with variation in dot size and dot pause. The scatter of some sets of data was increased because of outliers or systematic trends within the set.

Teardown Of A Low-Cost Laser Diode Package
Authors: David Rae, Pericles A. Kondos and K. Srihari

Abstract: Teardown of a Honeywell HFE 4086-001 VCSEL was undertaken with all notable features being photographed and documented. Materials used in the construction of the package were analyzed with EDS spectroscopy. EDS also revealed a relatively complicated method of attaching the pieces of the case. Component assembly variation was estimated from the measurements of 5 components.

Single Mode Laser Diode Packaging
Authors: Peter Borgesen and Pericles Kondos

Abstract: The development of optimized optoelectronics manufacturing processes may often require some understanding of the optics as well as of the mechanical and thermal design, materials, and process issues. This is certainly the case for the packaging of single mode laser diodes, where optical alignment and coupling plays a dominant role. Referring to a couple of current generic packages for illustration we discuss some of the manufacturing issues involved as well as potential improvements. Topics addressed include alternatives in terms of package design and contents, optical alignment and coupling schemes, and the use of laser welding, soldering, and adhesives.

Common Processes For Passive Optical Component Manufacturing
Authors: Laurence A. Harvilchuck and Peter Borgesen

Abstract: Permeation of fiber optic communication systems at the end-user level (i.e. ‘fiber-in-the-home’) is predicated on a reliable supply of individual components, both active and passive. These components will most likely have price and volume targets that can only be satisfied by full automation of the packaging processes. Polarization dependent optical isolators are examples of a typical passive optical component that is widely deployed at all levels of the network. We will use these isolators as an example for our discussion.

Intelligent contemplation of the options available for isolator manufacturing requires comprehension of some basic optical principles and component functionality. It can then be seen that isolator performance is directly influenced by process variations and part tolerances. We present a discussion of issues relating to cost, ease of manufacturing, and automation, highlighting component design, materials selection, and intellectual property concerns.

Process Research Into The Automated Pin Transfer Of Adhesives For Optoelectronics Manufacturing
Authors: David Rae, Pericles A. Kondos and K. Srihari

Abstract: Studies were carried out to investigate the automated pin transfer of materials for electronics packaging, with a concentration in the deposition of optoelectronics adhesives. The impact of several process parameters on transfer was assessed, including transfer gap, pin diameter, dip length in reservoir, and the hold times and pin withdrawal speeds during pickup from the reservoir during transfer to the substrate. High speed video analysis and deposit volume measurements were used to study transfer behavior.

Increasing dip length, hold time, or withdrawal speed from the reservoir increased the volume picked out of the reservoir by the transfer pin. At the substrate, transfer gap, hold time, and withdrawal speed all influenced the transfer behavior of the material.

It was found that introducing an appropriate gap between the tip of the pin and the substrate reduced the scatter of the deposit volumes in comparison to contact pin transfer. Control over several other parameters in both the pickup and transfer stages was also found to reduced variation in deposition when used to minimize the influence of material supported on the sides of the pin. Use of a low surface energy coating on the pin, which in theory ought to reduce scatter by not allowing any material to remain on the sides of the pin revealed several drawbacks in practice.

Material issues investigated included deposit mass loss after placement and property changes that affected the volume deposited.

Using the optimized techniques described in this report, uniform volumes as small as 0.4 nl were placed with a variation in the deposits being as low as 1.3 % by volume.

Stability Of An Optical Component In Adhesive Cure
Author: Pericles A. Kondos

Abstract: Several hundred silicon die were attached on FR-4 boards with a Loctite silver-filled epoxy. The locations of the die on the board were measured with an automatic CMM before and after cure, to determine if curing caused any shifts in x, y, or angle. Statistics of the shifts was generated for each board. The tilt of the die relatively to their local region of the board was measured as well.

Attachment Processes With Eutectic Au80sn20 Solder
Author: Pericles A. Kondos

Abstract: Experiments were performed with both preforms of eutectic Au-Sn solder and multilayered structures of Au and Sn, with the aim of achieving soldering on gold without the need of scrubbing and forming gas. The way surface oxides affect the behavior of the preforms was studied in more detail. The change in the distribution of Sn in multilayers that were subjected to prolonged heating was determined and a piece of multilayer was successfully soldered on a gold-covered substrate.

Au/Sn Soldering
Author: Eric Cotts

Abstract: The metallurgy of eutectic Au80Sn20 and near eutectic Au-Sn soldering is reviewed with emphasis on the attachment of optoelectronics devices.

Burst-Stripping Of Optical Fibers
Authors: Antonio Prats, Kaustubh R. Nagarkar and K. Srihari

Abstract: A novel non-contact process for stripping optical fibers from 3SAE Technologies, Inc., was examined. This “burst technology” uses a burst of hot air to burn the coating off the fiber without damaging the glass.

The process seems to offer advantages over traditional stripping methods. Tensile testing of non-spliced fibers showed that the burst-stripped fibers had strengths near those of pristine, un-damaged fibers. Traditionally stripped fibers are much weaker. For spliced fibers, the burst-stripped fibers were a little stronger than the traditionally stripped ones, but both groups were much weaker than the pristine fibers. It was also seen that the recoating process is not likely to introduce any significant defects.

On The Interpretation Of Dynamic Tensile Tests Of Optical Fibers
Authors: P. Borgesen, Kaustubh R. Nagarkar and K. Srihari

Abstract: Mechanical testing of optical fibers would be meaningless without some, often implicit, interpretation in terms of life or performance in service. At a minimum we need a feeling for the level of importance of observed differences between, say, fibers exposed to different processes or handling conditions. Of course process and design guidelines based on the, necessarily quite extreme, extrapolation of accelerated test results to service conditions require a mechanistically based quantitative expression for the rate of damage evolution.

Recent comparisons of life in static bending and static tension led to concerns with respect to current interpretations of accelerated tests. In the present work the dynamic tensile strengths of as-received (“pristine”) optical fibers were measured over a range of loading rates and ambient humidities. The results of this and the previous static tests are discussed in terms of alternate damage evolution (crack growth rate) expressions.

Damage And Failure Of Optical Fiber Pigtails In Handling
Authors: Kaustubh R. Nagarkar, Antonio Prats and K. Srihari

Abstract: Too often optoelectronics products prove unnecessarily fragile in handling, one recurring failure being breakage of the fiber where it attaches to the package. Heat cured adhesives are used to attach optical fibers to components such as optical connectors, isolators, or circulators. The objective of the present research is to identify some of the factors that may affect the reliability of the fibers embedded in adhesives. This study utilizes fibers attached to commercially available zirconia ferrules as well as fibers in model assemblies.

Effects Of Humidity On The Life Of Optical Fibers In Static Bending
Authors: Peter Borgesen, Kaustubh R. Nagarkar and K. Srihari

Abstract: Optical fibers are often mounted under some degree of bending, leading to fatigue crack growth under the influence of ambient humidity. Previous work suggested a stronger humidity dependence in static bending than in static tension. This would have both obvious and potentially more subtle but significant consequences for extrapolation of test results to life in service. The present work addresses the dependencies of crack growth and life on both humidity and bending stress for “pristine” optical fibers.

Life Of ‘Pristine’ Optical Fibers In Static Tension
Authors: Peter Borgesen, Kaustubh R. Nagarkar and K. Srihari

Abstract: Corning LEAF® single mode optical fibers as received directly from the manufacturer were tested for life in static tension. Observed dependencies on load and ambient humidity were compared to theoretical predictions and other experimental data. Results have obvious consequences for the extrapolation of accelerated test results to life in service.

Optoelectronics Packaging Research 2002
Author: Peter Borgesen

Abstract: The present report offers a brief summary of the optoelectronics packaging research activities within the 2002 Area Array Consortium. These included studies on assembly, Au-Sn soldering, optical adhesive properties, and optical fiber processing and reliability. Specific references are made to all individual progress reports for details.